Image sensors including conductive pixel separation structures

Patent metadata

Field	Value
Publication number	US-9524995-B2
Application number	US-201414191670-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Mar 4, 2013
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

An image sensor includes a substrate having adjacent pixel regions and respective photodiode regions therein, and a pixel separation portion including a trench extending into the substrate between the adjacent pixel regions. The trench includes a conductive common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench. A conductive interconnection is coupled to the common bias line and is configured to provide a negative voltage thereto. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. An image sensor, comprising:
a substrate comprising a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface, wherein the second surface is arranged to receive incident light;
a photoelectric conversion part in each of the pixel regions of the substrate;
a gate electrode in each of the pixel regions of the substrate for receiving signals from the photoelectric conversion part;
a pixel separation portion including a deep device isolation layer in the substrate that separates the pixel regions from each other, a common bias line extending along the deep device isolation layer in the deep device isolation layer, and a channel-stop region in contact with the deep device isolation layer;
a shallow device isolation layer in contact with the first surface and spaced apart from the deep device isolation layer, the shallow device isolation layer having a depth less than that of the deep device isolation layer; and
in plan view, an external-voltage-applying wire disposed at an end portion of the common bias line and electrically connected to the common bias line,
wherein the common bias line is configured to be applied with a negative voltage, and wherein the channel-stop region is between the deep device isolation layer and the shallow device isolation layer.

2. The image sensor of claim 1 , wherein in plan view, the common bias line has a grid shape.

3. The image sensor of claim 1 , wherein the common bias line has a curved top or bottom surface.

4. The image sensor of claim 3 , wherein the common bias line is electrically isolated from the substrate.

5. The image sensor of claim 1 , wherein the common bias line has a top surface positioned adjacent the second surface and electrically connected to the external-voltage-applying wire that is configured to supply the negative voltage.

6. The image sensor of claim 5 , wherein the substrate further comprises an optical black region spaced apart from the pixel regions,
wherein the image sensor further comprises an optical black pattern provided on the optical black region, and
wherein the optical black pattern and the external-voltage-applying wire comprise a same material.

7. The image sensor of claim 5 , wherein the substrate further comprises a pad region spaced apart from the pixel region,
wherein the image sensor further comprises a through via provided through the pad region, and
wherein the through via and the external-voltage-applying wire comprise a same material.

8. An image sensor, comprising:
a substrate including adjacent pixel regions comprising respective photodiode regions therein, and an edge region;
a pixel separation portion comprising a trench extending into the substrate between the adjacent pixel regions, the trench including a common bias line therein and an insulating device isolation layer between the common bias line and surfaces of the trench;
in plan view, a line-shaped edge disposed at an end portion of the common bias line in the edge region, and disposed in the trench extending to the edge region from the pixel regions; and
a conductive interconnection disposed on the line-shaped edge to connect to the line-shaped edge and configured to provide a voltage to the common bias line,
wherein the trench including the common bias line therein defines a grid including the pixel regions therebetween in plan view,
wherein the trench including the common bias line therein does not extend completely through the substrate, and wherein the pixel separation portion further comprises:
a channel stop region between the insulating device isolation layer in the trench and a surface of the substrate, wherein the channel stop region comprises a conductivity type opposite to that of the respective photodiode regions.

9. The image sensor of claim 8 , wherein the surface of the substrate is opposite a light-receiving surface thereof.

10. The image sensor of claim 9 , wherein the pixel separation portion further comprises:
a shallow trench isolation region between the channel stop region and the surface of the substrate, wherein the channel stop region continuously extends from the insulating device isolation layer in the trench to the shallow trench isolation region.

11. The image sensor of claim 10 , wherein a depth of the shallow trench isolation region is less than that of the insulating device isolation region.

12. The image sensor of claim 9 , wherein the insulating device isolation layer includes a sub insulating portion horizontally protruding from an upper sidewall of the insulating device isolation layer adjacent to the surface of the substrate.

13. The image sensor of claim 1 , wherein the gate electrode includes a protruding portion positioned on the substrate and a buried portion inserted into the substrate.

14. The image sensor of claim 1 , further comprising a doped ground region disposed at one side of the gate electrode in each of the pixel regions of the substrate.

15. The image sensor of claim 1 , wherein the common bias line includes an undoped polysilicon layer, a doped polysilicon layer, a metal silicide layer, or a metal-containing layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Koo Junemo
• Kim Namgil
• Moon Changrok
• Park Byungjun
• Shin Jongcheol

Classifications

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/8023

  Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery · CPC title

• H10F39/807 Primary

  Pixel isolation structures · CPC title

• H01L27/1464

  Electricity · mapped topic