Array substrate and method of manufacturing the same, and liquid crystal display screen

Patent metadata

Field	Value
Publication number	US-9524989-B2
Application number	US-201414436258-A
Country	US
Kind code	B2
Filing date	Aug 12, 2014
Priority date	Apr 4, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Embodiments of the present invention disclose an array substrate and a method of manufacturing the same, and a liquid crystal display screen. The array substrate comprises gate lines, data lines arranged to intersect the gate lines, common electrode signal lines, and a plurality of pixels defined by the gate lines and the data lines, wherein each pixel comprises a drive transistor, a pixel electrode connected with one of a source electrode and a drain electrode of the drive transistor while the other one of the source electrode and the drain electrode of the drive transistor is connected with the respective data line, and a common electrode electrically connected with the respective common electrode signal line, and, the common electrode signal lines and the gate lines are formed in the same layer and extend in the same direction as the gate lines, wherein each pixel further comprises a common electrode connection line formed in the same layer as the respective common electrode signal line and extending in a direction of the respective data line, and the common electrode connection line is electrically connected with the respective common electrode signal line and the respective common electrode. Embodiments of the present invention is made so that the pixel resistance value is reduced, reducing the phenomenon of partial green picture in the liquid crystal display screen as a whole.

First claim

What is claimed is:

1. An array substrate, comprising:
gate lines, data lines arranged to intersect the gate lines, common electrode signal lines, and a plurality of pixels units defined by the gate lines and the data lines, wherein each pixel unit comprises a drive transistor, a pixel electrode connected with one of a source electrode and a drain electrode of the drive transistor while the other one of the source electrode and the drain electrode of the drive transistor is connected with a respective data line, and a common electrode electrically connected with a respective common electrode signal line, the common electrode signal lines and the gate lines being formed in the same layer and the common electrode signal lines extending in the same direction as the gate lines,
wherein each pixel unit further comprises a common electrode connection line formed in the same layer as the respective common electrode signal line and extending in a direction of the respective data line, and the common electrode connection line is electrically connected with the respective common electrode signal line and the respective common electrode which are located within the same pixel unit as the common electrode connection line.

2. The array substrate according to claim 1 , wherein the common electrode connection line for a pixel unit is connected, via a through-hole and a jumper, to the common electrode signal line for a next row of pixel units.

3. The array substrate according to claim 2 , wherein the jumper and the pixel electrode are formed of the same material in the same layer.

4. The array substrate according to claim 2 , wherein the jumper is formed by stacking an auxiliary conductive layer and a layer where the pixel electrode is located.

5. The array substrate according to claim 1 , wherein the gate lines are made of metal materials or metal compound materials.

6. The array substrate according to claim 5 , wherein the gate lines are made of one of or any combination of neodymium aluminum, aluminum, copper, molybdenum, tungsten molybdenum and chromium.

7. The array substrate according to claim 1 , wherein the common electrode and the pixel electrode layer are made of one of indium zinc oxide and indium tin oxide or a combination of indium zinc oxide and indium tin oxide.

8. The array substrate according to claim 4 , wherein the auxiliary conductive layer is a metal layer, or a conductive layer of low resistivity.

9. A liquid crystal display screen comprising the array substrate according to claim 1 .

10. A method of manufacturing an array substrate, the method comprising:
forming a plurality of common electrodes on a substrate;
depositing a gate layer on the substrate formed with the common electrodes, and etching the gate layer to form a gate pattern, wherein the gate pattern comprises gate lines, common electrode signal lines and common electrode connection lines, wherein the common electrode signal lines and the gate lines extend in the same direction; and
depositing in order and correspondingly etching an active layer, a source-drain electrode layer, a passivation layer and a pixel electrode layer so as to form a plurality of drive transistors, data lines intersecting the gate lines, and a plurality of pixel electrodes each of which is connected with one of a source electrode and a drain electrode of the respective drive transistor, the other one of the source electrode and the drain electrode of the drive transistor being connected with the respective data line;
wherein the plurality of drive transistors, the plurality of pixel electrodes and the plurality of common electrodes compose a plurality of pixel units, and the common electrode connection lines extend in a direction of the data lines and is electrically connected with the respective common electrode signal line and the respective common electrode which are located within the same pixel unit as the common electrode connection line.

11. A method of manufacturing an array substrate, the method comprising:
forming common electrodes on a substrate;
depositing a gate layer on the substrate formed with the common electrodes, and etching the gate layer to form a gate pattern, wherein the gate pattern comprises gate lines, common electrode signal lines, a through-hole region and common electrode connection lines, wherein the common electrode signal lines and the gate lines extend in the same direction, and the common electrode connection lines, the common electrode signal lines and the common electrodes are electrically connected with one another;
depositing in order and correspondingly etching an active layer, a source-drain electrode layer and a passivation layer so as to form a plurality of drive transistors and data lines intersecting the gate lines, one of a source electrode and a drain electrode of each drive transistor being connected with the respective data line;
depositing and etching a conductive layer to form a first layer of a jumper; and
depositing and etching a pixel electrode layer to form a pixel electrode layer pattern, wherein the pixel electrode layer pattern comprises a second layer of the jumper completely overlapped with the first layer of the jumper, and a plurality of pixel electrodes each of which is connected with the other one of the source electrode and the drain electrode of the respective drive transistor;
wherein the plurality of drive transistors, the plurality of pixel electrodes and the plurality of common electrodes compose a plurality of pixel units, and the common electrode connection lines extend in a direction of the data lines; and
wherein the first layer of the jumper connects the through hole region and a common electrode signal line corresponding to a next row of pixel units.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Yang Tong
• Wang Guolei

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/13439

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title