Microelectronic interconnect element with decreased conductor spacing

Patent metadata

Field	Value
Publication number	US-9524947-B2
Application number	US-201414557120-A
Country	US
Kind code	B2
Filing date	Dec 1, 2014
Priority date	Jul 9, 2008
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A microelectronic interconnect element can include a plurality of first metal lines and a plurality of second metal lines interleaved with the first metal lines. Each of the first and second metal lines has a surface extending within the same reference plane. The first metal lines have surfaces above the reference plane and remote therefrom and the second metal lines have surfaces below the reference plane and remote therefrom. A dielectric layer can separate a metal line of the first metal lines from an adjacent metal line of the second metal lines.

First claim

The invention claimed is:

1. A method of forming a microelectronic interconnect element, comprising:
(a) given a layered element including a first thin exposed metal layer having a first thickness, a second exposed metal layer having a second thickness substantially greater than the first thickness, and a removable layer sandwiched between the first thin exposed metal layer and second exposed metal layers, plating a plurality of first metal lines onto a first surface of the first thin exposed metal layer;
(b) forming a dielectric layer overlying the plurality of first metal lines;
(c) removing at least the second exposed metal layer and the removable layer to expose a second surface of the first thin exposed metal layer;
(d) plating a plurality of second metal lines onto the second surface of the first thin exposed metal layer; and
(e) removing at least a portion of the first thin exposed metal layer exposed between the plurality of first metal lines and plurality of second metal lines.

2. The method of forming the microelectronic interconnect element as claimed in claim 1 , wherein a pitch between a metal line of the plurality of first metal lines and an adjacent metal line of the plurality of second metal lines is smaller than a first pitch between the plurality of first metal lines obtained by plating and is smaller than a second pitch between the plurality of second metal lines obtained by plating.

3. The method of forming the microelectronic interconnect element as claimed in claim 2 , wherein the first pitch is equal to at least twice a width of one of the plurality of first metal lines, and second pitch is equal to at least twice a width of one of the plurality of second metal lines, such that, in a direction of the widths of the plurality of first metal lines, edges of at least some of the plurality of first metal lines are insulated and spaced from edges of at least some of the plurality of second metal lines by less than the width of one of the plurality of first metal lines.

4. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the edges of the at least some of the plurality of first metal lines are insulated and spaced from the edges of the at least some of the plurality of second metal lines by less than 10% of the width of one of the plurality of first metal lines.

5. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are less than about 60 microns.

6. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are at most about 20 microns.

7. The method of forming the microelectronic interconnect element as claimed in claim 3 , wherein the widths of the plurality of first metal lines and plurality of second metal lines are uniform and are at most about 10 microns.

8. The method of forming the microelectronic interconnect element as claimed in claim 1 , wherein each of the plurality of first metal lines has edges extending between upper and lower surfaces of such first metal line and a width between the edges, and each of the plurality of second metal lines has edges extending between upper and lower surfaces of such second metal line and a width between the edges, and a spacing between the edge of one of the plurality of first metal lines and an adjacent edge of one of the plurality of second metal lines is smaller than the widths of the adjacent ones of the pluralities of first and second metal lines.

9. The method of forming the microelectronic interconnect element as claimed in claim 1 , wherein the dielectric layer is formed by pressing a dielectric material onto the first plurality of metal lines, such that portions of the dielectric layer separate the plurality of first metal lines from one another.

Assignees

• Invensas Corp

Inventors

• Ryu Chang Myung
• Endo Kimitaka
• Haba Belgacem
• Kubota Yoichi

Classifications

• H10W70/6565

  recessed into the surface of the package substrates, interposers, or redistribution layers · CPC title

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title