Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9524925-B2
Application number	US-201615097093-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Jun 29, 2012
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

There is provided a method for manufacturing a semiconductor device including a first semiconductor base substrate, a second semiconductor base substrate that is bonded onto a first surface side of the first semiconductor base substrate, a through electrode that is formed to penetrate from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate, and an insulation layer that surrounds a circumference of the through electrode formed inside the first semiconductor base substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device including a through electrode that penetrates a first semiconductor base substrate, the method comprising:
forming an insulation layer that surrounds a circumference of a position at which the through electrode is formed, on a first surface of the first semiconductor base substrate;
bonding a second semiconductor base substrate to a first surface side of the first semiconductor base substrate;
forming an opening portion that penetrates from a second surface side of the first semiconductor base substrate to a wiring layer on the second semiconductor base substrate within a range surrounded by the insulation layer; and
forming the through electrode inside the opening portion.

2. The method of manufacturing a semiconductor device according to claim 1 , further comprising:
etching the first semiconductor base substrate within the range surrounded by the insulation layer, and then etching the first semiconductor base substrate remaining in an inner wall surface of the insulation layer in the step of forming the opening portion.

3. The method of manufacturing a semiconductor device according to claim 1 , comprising:
forming a first conductive layer in a wiring layer on the first surface of the first semiconductor base substrate,
wherein, as part of forming the opening portion, an opening portion is formed in the first conductive layer such that an opening on the second surface side of the first semiconductor base substrate is large and an opening on the first surface side of the first semiconductor base substrate is small.

4. The method of manufacturing a semiconductor device according to claim 1 , comprising:
selectively etching the first semiconductor base substrate in the range surrounded by the insulation layer; and
etching a part of an inner surface side of the insulation layer.

5. The method of manufacturing a semiconductor device according to claim 1 , comprising:
forming a first conductive layer in a wiring layer on the first surface of the first semiconductor base substrate, and forming an electrode protective layer between the insulation layer and the first conductive layer,
wherein forming the opening portion includes a step of etching the first semiconductor base substrate in the range surrounded by the insulation layer and a step of etching the portion from the electrode protective layer to the wiring layer on the second semiconductor base substrate.

6. The method of manufacturing a semiconductor device according to claim 5 , wherein, in forming the electrode protective layer, the electrode protective layer is formed such that the edge portion on an opening side of the electrode protective layer protrudes more in a center direction of the opening portion than the edge portion on an opening side of the insulation layer.

7. The method of manufacturing a semiconductor device according to claim 5 , wherein the electrode protective layer and the first conductive layer are formed in conjunction with the wiring layer on the first surface of the first semiconductor base substrate.

Assignees

• Sony Corp

Inventors

• Wakiyama Satoru
• Okamoto Masaki
• Ooka Yutaka
• Shohji Reijiroh
• Zaizen Yoshifumi
• Nagahata Kazunori
• Haneda Masaki

Classifications

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title