Device with Through-Substrate Via Structure and Method for Forming the Same
US-2015061147-A1 · Mar 5, 2015 · US
Dielectric cover for a through silicon via
US9524924B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9524924-B2 |
| Application number | US-201514967965-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 14, 2015 |
| Priority date | Oct 15, 2014 |
| Publication date | Dec 20, 2016 |
| Grant date | Dec 20, 2016 |
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Abstract
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An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, the structure comprising: a first dielectric layer covering a barrier layer and adjacent a topographical semiconductor feature, wherein the topographical semiconductor feature has a void area; a patterned second dielectric layer covering the void area of the topographical semiconductor feature and at least one portion of the first dielectric layer; and a first metal layer covering a portion of the topographical semiconductor fe…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9524924B2 cover?
- An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one po…
- Who is the assignee on this patent?
- Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 20 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).