Memory cell having closed curve structure

Patent metadata

Field	Value
Publication number	US-9524780-B2
Application number	US-201114000620-A
Country	US
Kind code	B2
Filing date	Mar 15, 2011
Priority date	Mar 15, 2011
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A memory cell including a drain, a channel, and a floating gate. The channel surrounds the drain and includes a first rounded closed curve structure around the drain. The floating gate is situated over the channel and includes a second rounded closed curve structure over the channel.

First claim

What is claimed is:

1. An EPROM memory cell suitable for an EEPROM array, the EPROM memory cell comprising:
a drain including a top and a bottom, wherein the drain is formed of an N+ doped region;
a channel that surround the drain and includes a first rounded closed curve structure around an entire surface area of the drain including a surface area of the bottom of the drain, wherein the channel is formed of a P doped region, wherein the first rounded closed curve structure increases uniformity of the length of the channel throughout the width of the channel relative to a rectangular channel;
a control gate situated over the channel; and
a floating gate capacitively coupled to the control gate, wherein the floating gate is situated over the channel and includes a second rounded closed curve structure over the channel to form the EPROM memory cell.

2. The EPROM memory cell of claim 1 , wherein the channel is elliptically shaped and the floating gate is elliptically shaped.

3. The EPROM memory cell of claim 2 , wherein the channel is circular and the floating gate is circular.

4. The EPROM memory cell of claim 1 , wherein the channel has multiple straight sides and at least one exterior rounded corner.

5. The EPROM memory cell of claim 1 , comprising a silicon dioxide layer between the channel and the floating gate.

6. The EPROM memory cell of claim 1 , wherein the second rounded closed curve structure increases uniformity of the length of the floating gate throughout the width of the floating gate relative to a rectangular floating gate.

7. The EPROM memory cell of claim 1 , comprising a source that surrounds the channel.

8. An EPROM array, comprising:
EPROM cells disposed in rows and columns, wherein each EPROM cell includes:
a source;
a drain having a top and a bottom and sides between the top and the bottom, wherein the drain is formed of an N+ doped region;
a channel that surrounds the drain on the sides, wherein the channel includes a first closed curve structure an entire surface area of the drain including a surface area of the bottom of the drain and a substantially uniform channel length throughout the width of the channel wherein the channel is formed of a P doped region, wherein in each EPROM cell the first closed curve structures improve programming efficiency over a rectangular channel EPROM cell;
a control gate situated over the channel; and
a floating gate capacitively coupled to the control gate, wherein the floating gate is situated over the channel, wherein the floating gate includes a second closed curve structure and a substantially uniform floating gate length throughout the width of the floating gate.

9. The EPROM array of claim 8 , wherein in each EPROM cell the channel is situated between the source and the drain.

10. The EPROM array of claim 9 , wherein in each EPROM cell the source surrounds the channel.

11. The EPROM array of claim 8 , wherein in each EPROM cell the channel is elliptically shaped and the floating gate is elliptically shaped.

12. The EPROM array of claim 8 , wherein in each EPROM cell the second closed curve structures improve programming efficiency over a rectangular floating gate EPROM cell.

13. A method of programming an EPROM cell, comprising:
providing a drain having a top and a bottom and sides between the top and the bottom wherein the drain is formed of an N+ doped region;
providing a channel having a first rounded closed curve structure that surrounds an entire surface area of the sides of the drain and a surface area of the bottom of the drain wherein the channel is formed of a P doped region;
providing a control gate situated over the channel; and
injecting hot carriers into a circular floating gate capacitively coupled to the control gate and having a second rounded close curve structure situated over the channel, wherein the channel and the circular floating gate improve programming efficiency over a rectangular channel and rectangular floating gate EPROM cell, wherein the channel provides a preprogramming EPROM ratio that is more centered around a specified value and reduced as compared to the preprogramming EPROM ratio provided via the rectangular channel EPROM cell.

14. The method of claim 13 , wherein programming efficiency is improved twenty percent over the rectangular channel and rectangular floating gate EPROM cell.

15. The method of claim 13 , wherein the circular floating gate provides a preprogramming EPROM ratio that is more centered around a specified value and reduced as compared to the preprogramming EPROM ratio provided via the rectangular floating gate EPROM cell.

Assignees

• Villavelez Reynaldo V
• Mikulan Paul I
• Hewlett Packard Development Co Lp

Inventors

• Villavelez Reynaldo V
• Mikulan Paul I

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• B41J2/04586

  controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type · CPC title

• B41J2/04541

  Specific driving circuit · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title