Systems and methods for multi-dimensional equalization constraint

Patent metadata

Field	Value
Publication number	US-9524748-B2
Application number	US-201414563919-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 8, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for multi-dimensional signal equalization. In one case, a data processing system is discussed that includes: a first equalizer governed at least in part by a first coefficient; a second equalizer circuit governed at least in part by a second coefficient; and a constraint circuit operable to force a sum of at least the first coefficient and the second coefficient to equal a defined value.

First claim

What is claimed is:

1. A data processing system, the system comprising:
a first equalizer circuit, wherein operation of the first equalizer circuit is governed at least in part by a first coefficient;
a second equalizer circuit, wherein operation of the second equalizer circuit is governed at least in part by a second coefficient; and
a constraint circuit operable to force a sum of at least the first coefficient and the second coefficient to equal a defined value.

2. The system of claim 1 , wherein operation of the first equalizer circuit is governed at least in part by a third coefficient and operation of the second equalizer circuit is governed at least in part by a fourth coefficient, wherein the constraint circuit is incorporated as part of a coefficient adaptation circuit, and wherein the coefficient adaptation circuit is operable to modify the third coefficient and the fourth coefficient while maintaining the sum of at least the first coefficient and the second coefficient equal to the defined value.

3. The system of claim 1 , wherein the defined value is programmable.

4. The system of claim 1 , wherein operation of the first equalizer circuit is further governed by a third coefficient, wherein operation of the second equalizer circuit is further governed by a fourth coefficient, and wherein the constraint circuit is further operable to force a sum of the first coefficient, the second coefficient, the third coefficient and the fourth coefficient to equal the defined value.

5. The system of claim 1 , wherein operation of the first equalizer circuit is further governed by a third coefficient, a fourth coefficient and a fifth coefficient; wherein operation of the second equalizer circuit is further governed by a sixth coefficient, a seventh coefficient and an eighth coefficient, and wherein the constraint circuit is further operable to force a sum of the first coefficient, the second coefficient, the third coefficient, the fourth coefficient, the fifth coefficient, the sixth coefficient, the seventh coefficient, and the eighth coefficient to equal the defined value.

6. The system of claim 1 , the system further comprising:
a comparator circuit operable to compare the sum with a threshold value; and
wherein the constraint circuit does not force the sum of at least the first coefficient and the second coefficient equal to the defined value when the comparator circuit indicates that the sum is greater than a threshold value.

7. The system of claim 6 , wherein the threshold value is programmable.

8. The system of claim 1 , the system further comprising:
a comparator circuit operable to compare the sum with a threshold value; and
wherein the constraint circuit does not force the sum of at least the first coefficient and the second coefficient equal to the defined value when the comparator circuit indicates that the sum is less than a threshold value.

9. The system of claim 8 , wherein the threshold value is programmable.

10. The system of claim 1 , wherein the system is implemented as part of an integrated circuit.

11. The system of claim 1 , wherein the system is implemented as part of a storage device.

12. The system of claim 11 , wherein the storage device comprises:
a storage medium; and
a read/write head assembly disposed in relation to the storage medium.

13. A method for data processing, the method comprising:
modifying a first coefficient value, a second coefficient value, a third coefficient value, and a fourth coefficient value based upon a feedback value;
constraining the first coefficient value and the second coefficient value such that a sum of at least the first coefficient value and the second coefficient value equals a defined value;
applying a first equalization algorithm by a first equalizer circuit guided by at least the first coefficient value and the third coefficient value to yield a first equalized output;
applying a second equalization algorithm by a second equalizer circuit guided by at least the second coefficient value and the fourth coefficient value to yield a second equalized output, wherein the second coefficient value and the fourth coefficient value are only used by the second equalizer circuit; and
combining the first equalized output and the second equalized output to yield a common equalized output.

14. The method of claim 13 , wherein the feedback value is based at least in part on a processing output selected from a group consisting of: a data decoder output, and a data detector output.

15. The method of claim 13 , the method further comprising:
constraining the first coefficient value, the second coefficient value, a fifth coefficient value, and a sixth coefficient value such that a sum of at the first coefficient value, the second coefficient value, the fifth coefficient value, and the sixth coefficient value equals the defined value;
wherein applying the first equalization algorithm by the first equalizer circuit is guided by at least the first coefficient value, the third coefficient value, and the fifth coefficient value; and
wherein applying the second equalization algorithm by the second equalizer circuit is guided by at least the second coefficient value, the fourth coefficient value, and the sixth coefficient value.

16. The method of claim 13 , the method further comprising:
constraining the first coefficient value, the second coefficient value, a fifth coefficient value, a sixth coefficient value, a seventh coefficient value, and an eighth coefficient value such that a sum of at the first coefficient value, the second coefficient value, the fifth coefficient value, the sixth coefficient value, the seventh coefficient value, and the eighth coefficient value equals the defined value;
wherein applying the first equalization algorithm by the first equalizer circuit is guided by at least the first coefficient value, the third coefficient value, the fifth coefficient value, and the seventh coefficient value; and
wherein applying the second equalization algorithm by the second equalizer circuit is guided by at least the second coefficient value, the fourth coefficient value, the sixth coefficient value, and the eighth coefficient value.

17. The method of claim 16 , wherein the method further comprises:
adding the first coefficient value, the second coefficient value, the fifth coefficient value, the sixth coefficient value, the seventh coefficient value, and the eighth coefficient value to yield a partial sum; and
comparing the partial sum with a threshold value, wherein the result of the constraining is only enforced when the partial sum is greater than a first threshold or less than a second threshold, and wherein the first threshold is greater than the second threshold.

18. The method of claim 17 , wherein the first threshold and the second threshold are programmable.

19. The method of claim 13 , wherein the defined value is programmable.

20. A data processing system, the system comprising:
a first means for equalizing data using at least a first coefficient;
a second means for equalizing data using at least a second coefficient, wherein the second coefficient is only used by the second means for equalizing; and
a means for constraining the first coefficient and the second coefficient such that a sum of the first coefficient and the second coefficient equals a constant.

Assignees

• Avago Technologies General Ip

Inventors

• Park Jongseung
• Mathew George

Classifications

• G11B5/035

  Equalising · CPC title

• G11B20/10046 Primary

  filtering or equalising, e.g. setting the tap weights of an FIR filter · CPC title

• G11B20/10055

  using partial response filtering when writing the signal to the medium or reading it therefrom · CPC title

• G11B20/10009

  Improvement or modification of read or write signals · CPC title

• G11B5/09

  Digital recording · CPC title