Method of driving a display panel, display panel driving apparatus for performing the method and display apparatus having the display panel driving apparatus

Patent metadata

Field	Value
Publication number	US-9524687-B2
Application number	US-201414315045-A
Country	US
Kind code	B2
Filing date	Jun 25, 2014
Priority date	Jan 22, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A method of driving a display panel includes respectively outputting first to j-th, where j is a natural number, gate signals to first to j-th gate lines disposed on a first area of the display panel during a load period when an image is displayed on the display panel due to an output of a data signal to the display panel, adjusting a blank gate voltage during a blank period between load periods to generate an adjusted blank gate voltage, generating a blank gate signal based on the adjusted blank gate voltage, and outputting the blank gate signal. Thus, display quality of a display apparatus may be improved.

First claim

What is claimed is:

1. A method of driving a display panel, the method comprising:
respectively outputting first to j-th, where j is a natural number, gate signals to first to j-th gate lines disposed on a first area of the display panel during a load period when an image is displayed on the display panel due to an output of a data signal to the display panel;
adjusting a blank gate voltage during a blank period between load periods to generate an adjusted blank gate voltage;
generating a blank gate signal based on the adjusted blank gate voltage; and
outputting the blank gate signal.

2. The method of claim 1 , wherein the generating the adjusted blank gate voltage comprises decreasing the blank gate voltage.

3. The method of claim 1 , wherein the outputting the first to j-th gate signals comprises:
adjusting a first gate voltage to generate an adjusted first gate voltage;
generating a first gate signal based on the adjusted first gate voltage; and
outputting the first gate signal to the first gate line disposed on the first area of the display panel.

4. The method of claim 3 , wherein the generating the adjusted first gate voltage comprises decreasing the first gate voltage.

5. The method of claim 1 , wherein the outputting the first to j-th gate signals comprises:
adjusting a j-th gate voltage to generate an adjusted j-th gate voltage;
generating the j-th gate signal based on the adjusted j-th gate voltage; and
outputting the j-th gate signal to the j-th gate line disposed on the first area of the display panel.

6. The method of claim 5 , wherein the generating the adjusted j-th gate voltage comprises decreasing the j-th gate voltage.

7. The method of claim 1 , wherein the outputting the first to j-th gate signals comprises:
respectively generating second to (j−1)-th gate signals from second to (j−1)-th gate voltage; and
respectively outputting the second to (j−1)-th gate signals to second to (j−1)-th gate lines disposed on the first area of the display panel.

8. The method of claim I, further comprising:
respectively outputting first to k-th, where k is a natural number, gate signal to first to k-th gate lines disposed on a second area different from the first area of the display panel during the load period.

9. The method of claim 8 , wherein the outputting the first to k-th gate signals comprises:
adjusting a first gate voltage to generate an adjusted first gate voltage;
generating a first gate signal based on the adjusted first gate voltage; and
outputting the first gate signal to the first gate line disposed on the second area of the display panel.

10. The method of claim 9 , wherein the generating the adjusted first gate voltage comprises decreasing the first gate voltage.

11. The method of claim 8 , the outputting the first to k-th gate signals comprises:
adjusting a k-th gate voltage to generate an adjusted k-th gate voltage;
generating the k-th gate signal based on the adjusted k-th gate voltage; and
outputting the k-th gate signal to the k-th gate line disposed on the second area of the display panel.

12. The method of claim 11 , wherein the generating the adjusted k-th gate voltage comprises decreasing the k-th gate voltage.

13. The method of claim 8 , wherein the outputting the first to k-th gate signals comprises:
respectively generating second to (k−1)-th gate signals from second to (k−1)-th gate voltage; and
respectively outputting the second to (k−1)-th gate signals to second to (k−1)-th gate lines disposed on the second area of the display panel.

14. A display panel driving apparatus comprising:
a gate voltage adjusting part configured to adjust a blank gate voltage to generate an adjusted blank gate voltage during a blank period between load periods when an image is displayed on a display panel due to an output of a data signal to the display panel;
a first gate driving part configured to respectively output first to j-th, where j is a natural number, gate signals to first to j-th gate lines disposed on a first area of the display panel during the load period, and configured to output a blank gate signal by generating the blank gate signal based on the adjusted blank gate voltage;
a first data driving part configured to output the data signal to a data line disposed on the first area of the display panel; and
a timing controlling part configured to output a gate start signal and a gate clock signal to the first gate driving part, and configured to output a data start signal and a data clock signal to the first data driving part.

15. The display panel driving apparatus of claim 14 , wherein the gate voltage adjusting part is configured to adjust a first gate voltage to generate an adjusted first gate voltage and is configured to adjust a j-th gate voltage to generate an adjusted j-th gate voltage, and
the first gate driving part is configured to generate the first gate signal based on the adjusted first gate voltage and is configured to generate the j-th gate signal based on the adjusted j-th gate voltage.

16. The display panel driving apparatus of claim 14 , further comprising:
a second gate driving part configured to respectively output first to k-th, where k is a natural number, gate signals to first to k-th gate lines disposed on a second area different from the first area of the display panel during the load period, and configured to output the blank gate signal by generating the blank gate signal based on the adjusted blank gate voltage; and
a second data driving part configured to output the data signal to a data line disposed on the second area of the display panel.

17. The display panel driving apparatus of claim 16 , wherein the gate voltage adjusting, part is configured to adjust a first gate voltage to generate an adjusted first gate voltage and is configured to adjust a k-th gate voltage to generate an adjusted k-th gate voltage, and
the second gate driving part is configured to generate the first gate signal based on th adjusted first gate voltage and is configured to generate the k-th gate signal based on the adjusted k-th gate voltage.

18. A display apparatus comprising:
a display panel configured to display an image; and
a display panel driving apparatus comprising:
a gate voltage adjusting part configured to adjust a blank gate voltage to generate an adjusted blank gate voltage during a blank period between load periods when the image is displayed on the display panel due to an output of a data signal to the display panel;
a first gate driving part configured to respectively output first to j-th, where j is a natural number, gate signals to first to j-th gate lines disposed on a first area of the display panel during the load period and configured to output a blank gate signal by generating the blank gate signal based on the adjusted blank gate voltage;
a first data driving part configured to output the data signal to a data line disposed on the first area of the display panel;
a second gate driving part configured to respectively output first to k-th, where k is a natural number, gate signals to first to k-th gate lines disposed on a second area different from the first area of the display panel during the load period and configured to output the blank gate signal by generating the blank gate signal based on the adjusted blank gate voltage;
a second data driving part configured to output the data signal to a data line disposed on the second area of the display panel; and
a timing controlling part configured to output a gate start signal and a gate clock signal to the

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Hak-Mo
• Nam Gwang-Ho
• Moon Hoi-Sik
• Chae Min-Yup
• Choi Jae-Seok

Classifications

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/04

  Structural and physical details of display devices · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title