Method and apparatus for bus lock assistance

Patent metadata

Field	Value
Publication number	US-9524263-B2
Application number	US-201213538463-A
Country	US
Kind code	B2
Filing date	Jun 29, 2012
Priority date	Jun 29, 2012
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

First claim

What is claimed is:

1. A method comprising:
detecting that a first instruction and a second instruction are locked instructions;
determining that execution of the first instruction and the second instruction each include imposing a bus lock; and
executing a bus lock assistance function in response to said determining, wherein the bus lock assistance function comprises:
preventing the bus lock from being imposed for the first instruction, and
permitting the bus lock to be imposed for the second instruction and causing a save of state information of an instruction execution pipeline that executes the second instruction.

2. The method of claim 1 wherein said determining that said execution of the first instruction and the second instruction each includes imposing the bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not cacheable.

3. The method of claim 1 wherein said determining that said execution of the first instruction and the second instruction includes imposing the bus lock includes determining that a memory type of each of the first instruction and the second instruction does not permit a cache lock.

4. The method of claim 1 wherein said determining that said execution of the first instruction and the second instruction includes imposing the bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not within a cache.

5. The method of claim 1 wherein said determining that said execution of the first instruction and the second instruction includes imposing the bus lock includes determining that an address of a data item to be fetched by each of the first instruction and the second instruction crosses a cache line boundary.

6. The method of claim 1 wherein said bus lock assistance function further comprises any of:
raising a flag to software;
preventing a bus lock protocol from being followed.

7. The method of claim 1 further comprising detecting that bus lock assistance has been enabled for the first instruction as a pre-condition to preventing the bus lock from being imposed for the first instruction, and detecting that bus lock assistance has been enabled for the second instruction as a pre-condition to permitting the bus lock to be imposed for the second instruction and causing the save of state information of the instruction execution pipeline that executes the second instruction.

8. An apparatus comprising:
instruction identification logic circuitry to identify when a first instruction and a second instruction are locked instructions;
first logic circuitry to determine if the first instruction and the second instruction are each to impose a bus lock when executed; and
second logic circuitry to trigger a bus lock assistance function when the first instruction and the second instruction are to each impose the bus lock when executed, wherein the bus lock assistance function is to:
prevent the bus lock from being imposed for the first instruction, and
permit the bus lock to be imposed for the second instruction and cause a save of state information of an instruction execution pipeline that executes the second instruction.

9. The apparatus of claim 8 wherein at least said instruction identification logic circuitry is embedded within an instruction execution pipeline.

10. The apparatus of claim 9 wherein said instruction identification logic circuitry is embedded within a stage of said instruction execution pipeline that performs instruction decoding.

11. The apparatus of claim 8 wherein said first logic circuitry is embedded within a memory execution unit of an instruction execution pipeline.

12. The apparatus of claim 8 wherein said second logic circuitry is embedded within a memory execution unit of an instruction execution pipeline.

13. The apparatus of claim 8 further comprising first register space that stores first information indicating if bus lock assistance has been enabled for the first instruction and the second instruction, and bus lock assistance logic circuitry to read said first information.

14. The apparatus of claim 13 further comprising second register space that stores second information to indicate whether the first instruction is a bus lock instruction and the second instruction is a bus lock instruction, said instruction identification logic circuitry to write to said second register space.

15. The apparatus of claim 8 further comprising third logic circuitry to:
detect that bus lock assistance has been enabled for the first instruction as a pre-condition to preventing the bus lock from being imposed for the first instruction, and
detect that bus lock assistance has been enabled for the second instruction as a pre-condition to permitting the bus lock to be imposed for the second instruction and causing the save of state information of the instruction execution pipeline that executes the second instruction.

16. The apparatus of claim 8 wherein said bus lock assistance function further comprises any of:
raising a flag to software;
preventing a bus lock protocol from being followed.

17. A non-transitory machine readable medium containing program instructions that when processed by a processing core causes a method to be performed, said method comprising:
detecting that a first instruction of a thread and a second instruction are locked instructions;
determining that execution of the first instruction and the second instruction includes imposing a bus lock; and
executing a bus lock assistance function in response to said determining, wherein the bus lock assistance function comprises:
preventing the bus lock from being imposed for the first instruction, and
permitting the bus lock to be imposed for the second instruction and causing a save of state information of an instruction execution pipeline that executes the second instruction.

18. The non-transitory machine readable medium of claim 17 wherein said determining that said execution of the first instruction and the second instruction each includes imposing the bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not cacheable.

19. The non-transitory machine readable medium of claim 17 wherein said determining that said execution of the first instruction and the second instruction includes imposing the bus lock includes determining that a memory type of each of the first instruction and the second instruction does not permit a cache lock.

20. The non-transitory machine readable medium of claim 17 wherein said determining that said execution of the first instruction and the second instruction includes imposing the bus lock includes determining that a data item to be fetched by each of the first instruction and the second instruction is not within a cache.

21. The non-transitory machine readable medium of claim 17 wherein said determining that said execution of the first instruction and the second instruction includes imposing the bus lock includes determining that an address of a data item to be fetched by each of the first instruction and the second instruction crosses a cache line boundary.

22. The non-transitory machine readable medium of claim 17 wherein said bus lock assistance function further comprises any of:
raising a flag to software; and
preventing a bus lock protocol from being followed.

23. The non-transitory machine r

Assignees

• Chappell Robert S
• Faistl John W
• Gartler Hermann W
• Tucknott Michael D
• Parathasarthy Rajesh S
• Burns David W
• Intel Corp

Inventors

• Chappell Robert S
• Faistl John W
• Gartler Hermann W
• Tucknott Michael D
• Parathasarthy Rajesh S
• Burns David W

Classifications

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/126

  with special data handling, e.g. priority of data or instructions, handling errors or pinning · CPC title

• G06F12/0842

  for multiprocessing or multitasking · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title