Adaptive process for data sharing with selection of lock elision and locking

Patent metadata

Field	Value
Publication number	US-9524195-B2
Application number	US-201414191581-A
Country	US
Kind code	B2
Filing date	Feb 27, 2014
Priority date	Feb 27, 2014
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

In a Hardware Lock Elision (HLE) Environment, predictively determining whether a HLE transaction should actually acquire a lock and execute non-transactionally, is provided. Included is, based on encountering an HLE lock-acquire instruction, determining, based on an HLE predictor, whether to elide the lock and proceed as an HLE transaction or to acquire the lock and proceed as a non-transaction; based on the HLE predictor predicting to elide, setting the address of the lock as a read-set of the transaction, and suppressing any write by the lock-acquire instruction to the lock and proceeding in HLE transactional execution mode until an xrelease instruction is encountered wherein the xrelease instruction releases the lock or the HLE transaction encounters a transactional conflict; and based on the HLE predictor predicting not-to-elide, treating the HLE lock-acquire instruction as a non-HLE lock-acquire instruction, and proceeding in non-transactional mode.

First claim

What is claimed is:

1. A computer program product for predictively determining an execution mode, the computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
in response to detecting, a transaction-starting prefix instruction added to a lock acquire instruction, by a processor having Hardware Lock Elision (HLE) support, beginning a transaction in lock elision mode, based on a count of mispredictions not exceeding a threshold number of failed transaction executions, otherwise entering non-transactional lock mode based on the count of mispredictions exceeding the threshold number of failed transaction executions;
in response to detecting a transaction-ending prefix instruction added to a lock release instruction, committing the transaction based on the processor not detecting an interference by an other processor, and incrementing a count of successful predictions; and
in response to the processor detecting the interference by the other processor, obtaining a lock, restarting the transaction in non-transactional lock mode, and incrementing the count of mispredictions.

2. The computer program product according to claim 1 , further comprising:
in response to accessing a memory region by a processor not having HLE support, invoking by the processor a conflict predictor wherein the processor enters lock elision mode based on a count of mispredictions not exceeding a threshold number of failed executions, and wherein the processor enters non-transactional lock mode based on the count of mispredictions exceeding the threshold number of failed executions;
incrementing the count of mispredictions and retrying the memory region access in non-transactional lock mode, based on the processor in lock elision mode detecting the interference by the other processor, and incrementing the count of successful predictions based on the processor not detecting the interference by the other processor; and
based on completion of the non-transactional lock mode memory region access, resetting, by the conflict predictor, the count of mispredictions and the count of successful predictions.

3. The computer program product according to claim 1 , wherein:
the prefix instruction is a processor hint, wherein the processor hint includes: the prefix instruction, a compiler instruction to prefer non-transactional lock mode or lock elision mode, and a calculated estimated relative cost of executing in non-transactional lock mode or lock elision mode.

4. A computer system for predictively determining an execution mode, the computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, the method comprising:
in response to detecting, by a processor having Hardware Lock Elision (HLE) support, a transaction-starting prefix instruction added to a lock acquire instruction, beginning a transaction in lock elision mode, based on a count of mispredictions not exceeding a threshold number of failed transaction executions, otherwise entering non-transactional lock mode based on the count of mispredictions exceeding the threshold number of failed transaction executions;
in response to detecting a transaction-ending prefix instruction added to a lock release instruction, committing the transaction based on the processor not detecting an interference by an other processor, and incrementing a count of successful predictions; and
in response to the processor detecting the interference by the other processor, obtaining a lock, restarting the transaction in non-transactional lock mode, and incrementing the count of mispredictions.

5. The computer system according to claim 1 , further comprising:
in response to accessing a memory region by a processor not having HLE support, invoking by the processor a conflict predictor wherein the processor enters lock elision mode based on a count of mispredictions not exceeding a threshold number of failed executions, and wherein the processor enters non-transactional lock mode based on the count of mispredictions exceeding the threshold number of failed executions;
incrementing the count of mispredictions and retrying the memory region access in lock mode, based on the processor in lock elision mode detecting the interference by the other processor, and incrementing the count of successful predictions based on the processor not detecting the interference by the other processor; and
based on completion of the non-transactional lock mode memory region access, resetting, by the conflict predictor, the count of mispredictions and the count of successful predictions.

6. The computer system according to claim 4 , wherein:
the prefix instruction is a processor hint, wherein the processor hint includes: the prefix instruction, a compiler instruction to prefer non-transactional lock mode or lock elision mode, and a calculated estimated relative cost of executing in non-transactional lock mode or lock elision mode.

Assignees

• IBM

Inventors

• Gschwind Michael Karl
• Michael Maged M
• Salapura Valentina
• Shum Chung-Lung K

Classifications

• G06F11/3419

  by assessing time · CPC title

• G06F9/526 Primary

  Mutual exclusion algorithms · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F11/1441

  Resetting or repowering · CPC title

• G06N5/02

  Knowledge representation; Symbolic representation · CPC title