Load balancing in a system with multi-graphics processors and multi-display systems

Patent metadata

Field	Value
Publication number	US-9524138-B2
Application number	US-64905909-A
Country	US
Kind code	B2
Filing date	Dec 29, 2009
Priority date	Dec 29, 2009
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

In typical embodiments a three GPU configuration is provided comprising three discrete video cards, each connected to a standard monitor placed horizontally for a 3× horizontal resolution. In this configuration, depending on the load on each GPU, the vertical split lines are dynamically adjusted. To adjust the load balancing according to these virtual split lines, the rendering clip rectangle of each GPU is adjusted, in order to reduce the number of pixels rendered by the heavily loaded GPU. These split lines define the boundary of the scene to be rendered by each GPU, and, according to some embodiments, may be moved horizontally. Thus for example if a GPU has a more complex rendering clip polygon to render than the other GPUs, the neighboring GPUs may render the rendering clip polygon it displays plus a portion of the rendering clip polygon to be displayed by heavily loaded GPU. The assisting GPUs transmit to the heavily loaded GPU the portion of the rendering clip polygon to be displayed by GPU via the chipset with a peer-to-peer protocol or through a communication bus. The split line is dynamically adjusted after each scene.

First claim

What is claimed is:

1. A method for load balancing display data in a system comprising a plurality of graphical processing units (GPUs) comprised in a plurality of graphics processing subsystems configured to present a contiguous display area, the method comprising:
identifying a first GPU of a plurality of GPUs having a heavier processing load than a second GPU of the plurality of GPUs for the next scene following a first scene of a plurality of scenes based on feedback data;
estimating a re-apportionment of a plurality of virtual split lines of a first frame of the next scene corresponding to the first GPU and a second frame of the next scene corresponding to the second GPU such that the respective loads are rendered by each of the plurality of GPUs at substantially equivalent times by removing sub-portions from the first frame and appending the sub-portions of the first frame to the second frame;
rendering the first and second frames according to the re-apportionment, the sub-portions of the first frame being rendered in the second GPU;
transferring the sub-portions of the first frame back to the first GPU after rendering is performed;
combining the sub-portions of the first frame with a remaining portion of the first frame rendered in the first GPU; and
presenting the first frame from a first control logic module comprised in a first graphics processing subsystem corresponding to the first GPU to a first display device coupled to the first GPU, and the second frame from a second frame buffer using a second control logic module comprised in a second graphics processing subsystem corresponding to the second GPU to a second display device coupled to the second GPU.

2. The method of claim 1 , wherein the feedback data comprises feedback data corresponding to the first scene rendered by at least a first one of the plurality of graphics processors and a second one of the plurality of graphics processors, the feedback data comprising respective rendering times for the first and second graphics processors to render a first and second rendering clip polygons of the plurality of frames comprising the scene.

3. The method of claim 2 , wherein the identifying further comprises:
comparing the respective rendering times to determine whether an imbalance exists between respective loads of the first and second graphics processors, the respective loads corresponding to the first and second rendering clip polygons of the scene, respectively.

4. The method according to claim 1 , wherein presenting the first frame to a first display device coupled to the first GPU and the second frame to a second display device coupled to the second GPU comprises:
synchronizing the next scene among the plurality of graphics processors.

5. The method of claim 1 , wherein the plurality of graphics processors comprises a plurality of frame buffers.

6. The method of claim 5 , wherein the transferring image data of the appended sub-portions rendered by the plurality of graphics processors not coupled to the first display device comprises copying the image data from the frame buffers of the plurality of graphics processors not coupled to the first display device into a frame buffer of the graphics processor coupled to the first display device.

7. The method of claim 1 , wherein the plurality of display devices comprises three display devices.

8. The method of claim 1 , wherein the plurality of display devices are oriented to display a single contiguous horizontal display area.

9. The method of claim 1 , wherein feedback data for a rendering clip polygon of a scene comprises timestamp data generated by the graphics processor rendering the portion of the rendering clip polygon.

10. The method of claim 1 , wherein the estimating a re-apportionment further comprises estimating a time corresponding to the transferring of the rendered image data from the frame buffers of the plurality of graphics processors not coupled to the first display device to the frame buffer of the graphics processor coupled to the first display device.

11. The method of claim 1 , further comprising applying a dampening function that restricts the estimated re-apportionment beyond a threshold.

12. The method of claim 3 , wherein an imbalance is determined when a disparity between the respective rendering times exceeds a threshold.

13. The method of claim 1 , wherein the transferring the plurality of sub-portions is performed via a communication bus communicatively coupling the plurality of graphics processors.

14. The method of claim 1 , wherein the transferring the sub-portions of the first frame comprises transferring the sub-portion of the first frame via a chipset comprising the plurality of graphics processing units with a peer-to-peer protocol.

15. The method of claim 1 , wherein the transferring the sub-portions of the first frame comprises transferring a portion of the first rendering clip polygon.

16. The method of claim 1 , wherein the re-apportioning of the respective virtual split lines is performed after each scene of the plurality of scenes.

17. A load balanced graphics processing system comprising:
a plurality of display devices;
a plurality of graphics processors comprised in a corresponding plurality of graphics subsystems and respectively coupled to display devices of the plurality of display devices, the plurality of graphics processors being configured to operate in parallel to render a single contiguous display area apportioned by a plurality of virtual split lines into a plurality of frames corresponding to the plurality of display devices;
a plurality of frame buffers comprised in the plurality of graphics processing subsystems for storing image data;
a plurality of control logic modules comprised in the plurality of graphics processing subsystems for communicating pixel data from a frame buffer of a graphics processor to a display device corresponding to the graphics processors; and
a plurality of graphics driver modules configured to determine, based on feedback data generated by the plurality of graphics processors, an imbalance between respective loads corresponding to the plurality of frame and, in response to detecting an imbalance: to redistribute a plurality of sub-portions of the frame attributed to a heavily loaded graphics processor among the other graphics processors of the plurality of graphics processors which are not the heavily loaded graphics processor for rendering, to transfer the sub-portions of the frame into a frame buffer of the heavily loaded graphics processor after rendering is performed, to combine the sub-portions of the frame with a remaining portions of the frame rendered by the heavily loaded graphics processor, and to present the plurality of frames to the plurality of display devices from the plurality of graphics processors respectively coupled to the plurality of display devices,
wherein, the feedback data comprises a plurality of flags, each flag corresponding to a frame of the plurality of frames and identifying the corresponding GPU performing the rendering for the frame.

18. The system of claim 17 , wherein the plurality of display devices comprises three display devices arranged according to a horizontal orientation.

19. The system of claim 17 , wherein the plurality of display devices comprises four display devices arranged to comprise four quadrants of a single contiguous rectangular display.

20. The system of claim 17 , wherein the feedback data comprises a plurality of timestamps generated by the plurality of graphic

Assignees

• Boucher Eric
• Diard Franck
• Nvidia Corp

Inventors

• Boucher Eric
• Diard Franck

Classifications

• G09G2360/08

  Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs · CPC title

• G06F9/5083

  Techniques for rebalancing the load in a distributed system · CPC title

• G09G2360/06

  Use of more than one graphics processor to process data before displaying to one or more screens · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F3/1438 Primary

  using more than one graphics controller · CPC title