Weaved electrical components in a substrate package core

US9521751B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9521751-B2
Application numberUS-201314085613-A
CountryUS
Kind codeB2
Filing dateNov 20, 2013
Priority dateNov 20, 2013
Publication dateDec 13, 2016
Grant dateDec 13, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit board pattern of conductive strands in a woven fabric. Next, the woven fabric is impregnated with a resin material to form an impregnated fabric, which is then cured to form a cured fabric. The upper and lower surfaces of the cured fabric are subsequently planarized. Planarizing segments and exposes ends of the wire, co-axial, and inductor pattern strands. Since the conductive strands were formed integrally within the planarized woven fabric, the substrate has a high mechanical stability and provides conductor strand based electrical components built in situ in the substrate package.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit board comprising: a circuit board pattern including a non-conductive board pattern of non-conductive strands woven between a component pattern of conductive strands; wherein the component pattern includes both of (a) co-axial strands having a dielectric material between a solid conductor material wire and an outer shield cylinder of conductor material surrounding the solid conductor material wire and (b) an inductor pattern of solid conductor material wires; cured resin impregnated within the circuit board pattern; a top planar surface of the circuit board pattern; a bottom planar surface of the circuit board pattern; a first plurality of contacts formed on the top planar surface and coupled to the solid conductor material wire and to the outer shield cylinder of conductor material of the co-axial strands; and a second plurality of contacts formed on the top planar surface and electrically coupled to the solid conductor material wires of the inductor pattern. 2. The circuit board of claim 1 , wherein the circuit board pattern includes the non-conductive strands woven in an X,Y direction between the conductive strands, and the conductive strands woven in a Z direction such that at least some of the conductive strands extend from a top surface to a bottom surface of the circuit board pattern. 3. The circuit board of claim 1 , wherein the non-conductive strands comprise a first set of vertically adjacent parallel non-conductive strands woven horizontally between the conductive strands in a first pattern, and a second set of vertically adjacent parallel non-conductive strands woven horizontally between the conductive strands in a second pattern that is a horizontal mirror image of the first pattern with respect to a vertical direction. 4. The circuit board of claim 1 , wherein the conductive strands include wire strands of solid conductor material wires. 5. The circuit board of claim 1 , wherein the inductor pattern includes a Toroid pattern formed by a solid conductor material wire; wherein the Toroid pattern has a Toroid inner diameter, a Toroid outer diameter, a Toroid top surface between the inner diameter and the outer diameter, and a Toroid bottom surface between the inner diameter and the outer diameter; and wherein the Toroid top surface is below a planarized top surface of the board, and the Toroid bottom surface is below a planarized bottom surface of the board. 6. The circuit board of claim 1 , wherein the inductor pattern includes an input wire extending to a first surface of the board, and an output wire extending to a second surface of the board. 7. The circuit board of claim 1 , wherein the circuit board pattern includes: a solid wire pattern of conductive strands of solid conductor material configured to pass power signals or ground signals; a co-axial pattern of conductive strands of co-axial conductor materials configured to pass high frequency data signals; and an inductor pattern having a Toroid pattern of wires of solid conductor material configured to filter out low frequency signals. 8. The circuit board of claim 1 , wherein the non-conductive strands are woven between the outer shield cylinder of conductor material and the inductor pattern of solid conductor material wires. 9. The circuit board of claim 8 , further comprising interconnects and traces formed in the circuit board pattern, wherein the interconnects and traces connect (1) the first plurality of the contacts to the co-axial strands and (2) the second plurality of the contacts to the inductor pattern. 10. A system for computing comprising: an integrated chip mounted on a substrate package, the a substrate package including: a circuit board pattern including a non-conductive board pattern of non-conductive strands woven between a component pattern of conductive strands; wherein the component pattern includes both of (a) co-axial strands having a dielectric material between a solid conductor material wire and an outer shield cylinder of conductor material surrounding the solid conductor material wire and (b) an inductor pattern of solid conductor material wires; cured resin impregnated within the circuit board pattern; a top planar surface of the circuit board pattern; a bottom planar surface of the circuit board pattern; a first plurality of contacts formed on the top planar surface and coupled to the solid conductor material wire and to the outer shield cylinder of conductor material of the co-axial strands; and a second plurality of contacts formed on the top planar surface and electrically coupled to the solid conductor material wires of the inductor pattern. 11. The system of claim 10 , wherein the circuit board pattern includes the non-conductive strands woven in an X,Y direction between the conductive strands, and the conductive strands woven in a Z direction such that at least some of the conductive strands extend from a top surface to a bottom surface of the circuit board pattern. 12. The system of claim 10 , wherein the non-conductive strands comprise a first set of vertically adjacent parallel non-conductive strands woven horizontally between the conductive strands in a first pattern, and a second set of vertically adjacent parallel non-conductive strands woven horizontally between the conductive strands in a second pattern that is a horizontal mirror image of the first pattern with respect to a vertical direction. 13. The system of claim 10 , wherein the conductive strands include wire strands of solid conductor material wires. 14. The system of claim 10 , wherein the inductor pattern includes a Toroid pattern formed by a solid conductor material wire; wherein the Toroid pattern has a Toroid inner diameter, a Toroid outer diameter, a Toroid top surface between the inner diameter and the outer diameter, and a Toroid bottom surface between the inner diameter and the outer diameter; and wherein the Toroid top surface is below a planarized top surface of the board, and the Toroid bottom surface is below a planarized bottom surface of the board. 15. The system of claim 10 , wherein the inductor pattern includes an input wire extending to a first surface of the board, and an output wire extending to a second surface of the board. 16. The system of claim 10 , wherein the circuit board pattern includes: a solid wire pattern of conductive strands of solid conductor material configured to pass power signals or ground signals; a co-axial pattern of conductive strands of co-axial conductor materials configured to pass high frequency data signals; and an inductor pattern having a Toroid pattern of wires of solid conductor material configured to filter out low frequency signals. 17. The system of claim 10 wherein the non-conductive strands are woven between the outer shield cylinder of conductor material and the inductor pattern of solid conductor material wires. 18. The system of claim 17 , further comprising interconnects and traces formed in the circuit board pattern, wherein the interconnects and traces connect (1) the first plurality of the contacts to the co-axial strands and (2) the second plurality of the contacts to the inductor pattern. 19. A circuit board comprising: a circuit board pattern including a non-conductive board pattern of non-conductive strands woven between a component pattern of conductive strands; wherein the component pattern includes one of (a) co-axial strands having a dielectric material between a solid conductor material wire and an outer shield cylinder of conductor material surrou

Assignees

Inventors

Classifications

  • Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components · CPC title

  • Special cross-section of a lead; Different cross-sections of different leads; Matching cross-section, e.g. matched to a land · CPC title

  • Cutting, sawing, milling or shearing · CPC title

  • fabric · CPC title

  • Coaxial layout · CPC title

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What does patent US9521751B2 cover?
A substrate package includes a woven fabric having electrically non-conductive strands woven between electrically conductive strands including wire strands, co-axial strands, and/or an inductor pattern of strands. The package may be formed by an inexpensive and high throughput process that first weaves the non-conductive strands (e.g., glass) between the conductive strands to form a circuit boa…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H05K1/038. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).