Multi-wire signaling with matched propagation delay among wire pairs

Patent metadata

Field	Value
Publication number	US-9521058-B2
Application number	US-201615097027-A
Country	US
Kind code	B2
Filing date	Apr 12, 2016
Priority date	Jun 25, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

First claim

What is claimed is:

1. An apparatus for multi-wire signaling, comprising:
a plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire; and
at least one delay element coupled to at least one of the plurality of wires,
wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and signal propagation times associated with wire pairs of the plurality of wires are equal to one another within a margin of error.

2. The apparatus of claim 1 , wherein the at least one delay element comprises a passive delay structure.

3. The apparatus of claim 1 , wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire.

4. The apparatus of claim 1 , wherein the at least one delay element comprises an active delay device.

5. The apparatus of claim 1 , wherein:
the at least one delay element comprises a programmable delay device; and
the apparatus further comprises a delay controller to generate at least one control signal to control a delay of the at least one delay element.

6. The apparatus of claim 1 , further comprising a driver circuit coupled to the plurality of wires and configured to, for a particular data transfer, drive a particular one of the wire pairs of the plurality of wires, whereby every other wire of the plurality of wires is in a high impedance state, wherein the driver circuit embodies the at least one delay element.

7. The apparatus of claim 1 , further comprising a receiver circuit coupled to the plurality of wires and configured to decode information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state.

8. The apparatus of claim 7 , wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver.

9. The apparatus of claim 1 , wherein the at least one delay element comprises a delay element coupled to at least one of the first outer wire or the second outer wire.

10. The apparatus of claim 1 , wherein the at least one middle wire comprises at least two middle wires.

11. A method for multi-wire signaling, comprising:
determining signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire; and
specifying a delay for at least one delay element coupled to at least one of the plurality of wires,
wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error.

12. The method of claim 11 , wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire.

13. The method of claim 11 , wherein:
the at least one delay element has a programmable delay; and
the specification of the delay comprises controlling the programmable delay of the at least one delay element.

14. The method of claim 11 , further comprising driving a particular one of the wire pairs of the plurality of wires for a particular data transfer, whereby every other wire of the plurality of wires is in a high impedance state.

15. The method of claim 11 , further comprising decoding information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state.

16. The method of claim 15 , wherein the information is decoded via a receiver circuit coupled to the plurality of wires, wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver.

17. The method of claim 11 , wherein the at least one delay element comprises a delay element coupled to at least one of the first outer wire or the second outer wire.

18. The method of claim 11 , wherein the at least one middle wire comprises at least two middle wires.

19. An apparatus for multi-wire signaling, comprising:
a communication interface circuit; and
a processing circuit configured to via the communication interface circuit:
determine signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least one middle wire, a first outer wire located adjacent to one side of the at least one middle wire, and a second outer wire located adjacent to another side of the at least one middle wire, and
specify a delay for at least one delay element coupled to at least one of the plurality of wires,
wherein the at least one delay element provides an amount of signal delay such that a signal propagation time associated with the at least one middle wire is less than a signal propagation time associated with at least one of the first outer wire or the second outer wire and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error.

20. The apparatus of claim 19 , wherein the at least one delay element comprises a wire of a defined length such that an overall length of the at least one middle wire is shorter than a length of the first outer wire and the second outer wire.

21. The apparatus of claim 19 , wherein:
the at least one delay element has a programmable delay; and
the specification of the delay comprises controlling the programmable delay of the at least one delay element.

22. The apparatus of claim 19 , the processing circuit further configured to drive a particular one of the wire pairs of the plurality of wires for a particular data transfer, whereby every other wire of the plurality of wires is in a high impedance state.

23. The apparatus of claim 19 , the processing circuit further configured to decode information for a particular data transfer based on a particular one of the wire pairs of the plurality of wires being driven, and every other wire of the plurality of wires being in a high impedance state.

24. The apparatus of claim 23 , wherein the information is decoded via a receiver circuit coupled to the plurality of wires, wherein the receiver circuit comprises at least one differential receiver and the at least one delay element is coupled to an output of the at least one differential receiver.

25. The apparatus of claim 23 , wherein the at lea

Assignees

• Qualcomm Inc

Inventors

• Pandey Shree Krishna
• Kundu Arun Chandra
• Wiley George Alan
• Lee Chulkyu

Classifications

• H04L7/0041

  Delay of data signal · CPC title

• H04B3/462 Primary

  Testing group delay or phase shift, e.g. timing jitter · CPC title

• H04L43/087 Primary

  Jitter · CPC title

• H04L25/0264

  Arrangements for coupling to transmission lines (duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878) · CPC title

• H04B3/542

  the information being in digital form · CPC title