Apparatus and method for high linearity tuning

Patent metadata

Field	Value
Publication number	US-9520904-B2
Application number	US-201314078686-A
Country	US
Kind code	B2
Filing date	Nov 13, 2013
Priority date	Nov 13, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A system that incorporates teachings of the subject disclosure may include, for example, a plurality of variable capacitors, a first set of resistors for applying a bias voltage to each variable capacitor of the plurality of capacitors, and a second set of resistors for providing a DC ground to each variable capacitor of the plurality of capacitors. The system can include one or more of multiple bias points, anti-parallel diodes, a choke inductor or a ground inductor. Other embodiments are disclosed.

First claim

What is claimed is:

1. A mobile communication device, comprising:
a transceiver;
an antenna coupled with the transceiver; and
a matching network coupled with the transceiver and the antenna, wherein the matching network comprises a plurality of variable capacitors connected in series, a first string of resistors for applying a bias voltage to each variable capacitor of the plurality of capacitors, and a second string of resistors for providing a DC ground to each variable capacitor of the plurality of capacitors, wherein the first string of resistors has a first bias point coupled to a voltage bias source via a first feed inductor, the first bias point corresponding to a node on the first string of resistors between selected adjacent resistors of the first string of resistors, and wherein a location of the first bias point along the first string of resistors is adjustable via a switching circuit that changes the location of the first bias point to a different node on the first string of resistors.

2. The mobile communication device of claim 1 , wherein the first string of resistors has one or more second bias points coupled to the voltage bias source via one or more second feed inductors, respectively.

3. The mobile communication device of claim 2 , wherein the plurality of variable capacitors is at least twenty four variable capacitors, and wherein the coupling of the first bias point and the one or more second bias points to the voltage bias source is via multiple outputs of a digital-to-analog converter, respectively.

4. The mobile communication device of claim 1 , wherein the first bias point is coupled to the voltage bias source via the first feed inductor without using a feed resistor.

5. The mobile communication device of claim 1 , wherein the matching network comprises at least one ground inductor coupled with the second string of resistors.

6. The mobile communication device of claim 5 , wherein the matching network comprises a ground resistor coupled in series with the at least one ground inductor.

7. The mobile communication device of claim 1 , wherein the plurality of variable capacitors includes alternating pairs of top variable capacitors and pairs of bottom variable capacitors, and wherein each second resistor of the second string of resistors is in parallel with a pair of adjacent top and bottom variable capacitors.

8. The mobile communication device of claim 1 , wherein the plurality of variable capacitors includes alternating pairs of top variable capacitors and pairs of bottom variable capacitors, and wherein each first resistor of the first string of resistors is in parallel with a pair of adjacent top variable capacitors or with a pair of adjacent bottom variable capacitors.

9. The mobile communication device of claim 1 , comprising:
a memory storing computer instructions; and
a processor coupled to the memory and the matching network, wherein the processor, responsive to executing the computer instructions, performs operations comprising:
providing biasing signals to the voltage bias source to enable adjusting of the plurality of variable capacitors via the first bias point to perform impedance matching, wherein the biasing signals are determined from at least one of a measured operational parameter of the mobile communication device or a determined use case of the mobile communication device.

10. A device, comprising:
a plurality of variable capacitors connected in series;
a first set of resistors for applying a bias voltage to each variable capacitor of the plurality of variable capacitors; and
a second set of resistors for providing a DC ground to each variable capacitor of the plurality of variable capacitors,
wherein the first set of resistors has one or more bias points, and
wherein the one or more bias points are coupled to a voltage bias source via one or more feed inductors, respectively,
wherein the one or more bias points are first and second bias points that are each coupled to the voltage bias source via a respective one of the one or more feed inductors and further comprising:
an anti-parallel diode sub-circuit located between the first and second bias points, wherein a feed resistor is positioned in parallel with the anti-parallel diode sub-circuit, and wherein the anti-parallel diode sub-circuit includes a first diode that is in an anti-parallel configuration with a second diode; and
a switching circuit operably coupled with the first set of resistors and with the one or more bias points, wherein the first and second bias points respectively correspond to first and second nodes between selected adjacent resistors of the first set of resistors, wherein a location of at least one of the first and second bias points along the first set of resistors is adjustable via the switching circuit that changes the location of the at least one of the first and second bias points between different pairs of resistors of the first set of resistors.

11. The device of claim 10 , comprising at least one ground inductor coupled with the second set of resistors.

12. The device of claim 11 , comprising a ground resistor coupled in series with the at least one ground inductor.

13. The device of claim 10 , wherein the plurality of variable capacitors include alternating pairs of top variable capacitors and pairs of bottom variable capacitors, and wherein each second resistor of the second set of resistors is in parallel with a pair of adjacent top and bottom variable capacitors.

14. The device of claim 10 , wherein the plurality of variable capacitors include alternating pairs of top variable capacitors and pairs of bottom variable capacitors, and wherein each first resistor of the first set of resistors is in parallel with a pair of adjacent top variable capacitors or with a pair of adjacent bottom variable capacitors.

15. A method, comprising:
determining, by a system including a processor, a desired insertion loss associated with a tunable component;
determining, by the system, a desired response time speed associated with the tunable component;
connecting a first string of resistors and a second string of resistors with a plurality of variable capacitors connected in series, wherein the first string of resistors is configured for applying a bias voltage to each variable capacitor of the plurality of capacitors, and wherein the second string of resistors is configured for providing a DC ground to each variable capacitor of the plurality of capacitors; and
connecting a voltage bias source to the first string of resistors at first and second bias points, the first and second bias points corresponding respectively to first and second nodes on the first string of resistors between selected adjacent resistors of the first string of resistors, wherein positioning of the first and second bias points along the first string of resistors is adjusted via a switching circuit based on the desired insertion loss and the desired response time speed, wherein the positioning of the first and second bias points changes between different pairs of resistors of the first string of resistors.

16. The method of claim 15 , wherein the connecting of the voltage bias source to the first string of resistors is via feed resistors, wherein the plurality of variable capacitors include alternating pairs of top variable capacitors and pairs of bottom variable capacitors, wherein each second resistor of the second string of resistors is in parallel with a pair of adjacent top and bottom variable capacitors, and wherein each first resistor of the first string of resistors is in parallel with a pair of adj

Assignees

• Blackberry Ltd

Inventors

• Horne Edward
• Boire Daniel Charles
• Greene Matthew Russell
• Oakes James

Classifications

• H04B1/406

  with more than one transmission mode, e.g. analog and digital modes · CPC title

• H04B1/18

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H03H7/40

  Automatic matching of load impedance to source impedance · CPC title

• H04B1/40

  Circuits · CPC title

• H04B1/0458 Primary

  Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H) · CPC title