Digital to analog converter, unit for the same, and method for using the same

Patent metadata

Field	Value
Publication number	US-9520892-B2
Application number	US-201514979521-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 29, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Disclosed herein is a digital-to-analog converter (DAC) including a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value. According to the present invention, distortion of the output of the DAC may be attenuated and loss of the output may be minimized by utilizing the RZ technique.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) comprising:
a clock driver for controlling a clock signal to provide an inverse delay clock signal to allow at least selective adjustment of a return to zero (RZ) section; and
a DAC core comprising at least two DAC units for receiving a digital input value, the clock signal and the inverse delay clock signal and providing an analog output value.

2. The DAC according to claim 1 , wherein the clock driver adjusts enablement and disablement of RZ.

3. The DAC according to claim 1 , wherein the DAC core comprises:
an RZ flip-flop for outputting 0 as a flip-flop output signal and an inverse flip-flop output signal such that the RZ section is established when both the clock signal and the inverse delay clock signal are 1;
a switch driver for outputting 0 as a reset signal when both the flip-flop output signal and the inverse flip-flop output signal are 0; and
an output unit comprising an RZ signal switch unit and an output signal switch unit, the RZ signal switch unit setting an output value to 0 in a section having the reset signal equal to 0 and the output signal switch unit providing a positive or negative output value in a section having the reset signal unequal to 0.

4. The DAC according to claim 1 , wherein the RZ section is adjusted by a signal constituted in 4 bits.

5. The DAC according to claim 1 , wherein the digital input value is obtained by converting an original digital input value through a dynamic element matching (DEM) circuit,
wherein the DEM circuit is adjustable to be turned on and off.

6. A digital-to-analog converter (DAC) unit comprising:
a return to zero (RZ) flip-flop for receiving a clock signal and an inverse delay clock signal delayed by an RZ section by converting the clock signal and outputting 0 as a flip-flop output signal and an inverse flip-flop output signal in the RZ section;
a switch driver for outputting 0 as a reset signal when both the flip-flop output signal and the inverse flip-flop output signal are 0; and
an output unit for outputting an output value of 0 in a section having the reset signal equal to 0 and outputting a positive or negative output value in a section having the reset signal unequal to 0.

7. The DAC unit according to claim 6 , wherein the RZ flip-flop is configured as hardware.

8. The DAC unit according to claim 7 , wherein the RZ flip-flop comprises:
a sense amplifier for outputting, when the clock signal corresponds to a rising edge, logic values of a digital input value and an inverse digital input value as a reset set signal and a sensing set signal and maintaining the logic values until a rising edge of a next clock signal appears; and
an RZ latch for outputting 0 as the flip-flop output signal and the inverse flip-flop output signal when the clock signal and the inverse delay clock signal are 1, and
outputting, when any one of the clock signal and the inverse delay clock signal is not 1,the flip-flop output signal and the inverse flip-flop output signal such that the flip-flop output signal complies with a value of the reset set signal, and the inverse flip-flop output signal complies with a value of the sensing set signal.

9. The DAC unit according to claim 6 , wherein the switch driver comprises an inverter for inverting the flip-flop output signal and the inverse flip-flop output signal and outputting final switch pair input data and inverse final switch pair input data.

10. The DAC unit according to claim 9 , wherein the switch driver comprises:
two reset switches having a power supply as a source, having the final switch pair input data and the inverse final switch pair input data as gates thereof, and having a reset signal output terminal for outputting the reset signal connected to a drain.

11. The DAC unit according to claim 6 , further comprising:
an RZ switch unit for outputting an output value of 0 in a section having the reset signal equal to 0; and
an output signal switch unit for outputting a positive or negative output value in a section having the reset signal unequal to 0.

12. The DAC unit according to claim 11 , wherein the RZ switch unit and the output signal switch unit are connected in parallel.

13. A method of operating a digital-to-analog converter (DAC) comprising a clock driver and a DAC core, the method comprising:
controlling, by the clock driver, a clock signal to provide an inverse delay clock signal for allow at least selective adjustment of a return to zero (RZ) section;
receiving, by the DAC core comprising at least two DAC units, the clock signal, the inverse delay clock signal, and a digital input value;
adjusting, by the DAC core, the RZ section based on the received clock signal and the received inverse delay clock signal; and
converting, by the DAC core, the digital input value based on the adjusted RZ section to output an analog output value.

14. The method according to claim 13 , wherein the RZ section is adjusted by comparing the clock signal and the inverse delay clock signal.

15. The method according to claim 13 , wherein a duration of time when both the clock signal and the inverse delay clock signal are 1 is the RZ section.

Assignees

• Gwangju Inst Science & Tech

Inventors

• Lee Min-Jae
• Kim Seong-Geon
• Kang Jae-Hyun

Classifications

• H03M1/74

  Simultaneous conversion · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03M1/0863

  of switching transients, e.g. glitches · CPC title