Delay structure for a memory interface

Patent metadata

Field	Value
Publication number	US-9520864-B2
Application number	US-201414298742-A
Country	US
Kind code	B2
Filing date	Jun 6, 2014
Priority date	Jun 6, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.

First claim

What is claimed is:

1. A method for delaying a signal, comprising:
receiving a first rising edge at an input;
in response to receiving the first rising edge, enabling an oscillator;
counting a number of oscillations of the oscillator;
outputting a second rising edge at an output if the number of oscillations reaches a predetermined number; and
in response to the number of oscillations reaching the predetermined number, disabling the oscillator until a third rising edge is received at the input.

2. The method of claim 1 , wherein the oscillator comprises a delay circuit, and enabling the oscillator comprises coupling an output of the delay circuit to an input of the delay circuit.

3. The method of claim 2 , wherein coupling the output of the delay circuit to the input of the delay circuit comprises coupling the output of the delay circuit to the output of the delay circuit through an inverter.

4. The method of claim 2 , wherein the delay circuit comprises a plurality of delay elements coupled in series.

5. The method of claim 2 , wherein disabling the oscillator comprises blocking the output of the delay circuit from the input of the delay circuit.

6. The method of claim 1 , further comprising, in response to receiving the first rising edge, transitioning the output from a high logic state to a low logic state.

7. The method of claim 1 , further comprising generating the first rising edge and the third rising edge using a reference clock, wherein the first rising edge and the third rising edge are spaced apart by one period of the reference clock or multiple periods of the reference clock.

8. An apparatus for delaying a signal, comprising:
means for receiving a first rising edge at an input;
means for enabling an oscillator in response to receiving the first rising edge;
means for counting a number of oscillations of the oscillator;
means for outputting a second rising edge at an output if the number of oscillations reaches a predetermined number; and
means for disabling the oscillator until a third rising edge is received at the input in response to the number of oscillations reaching the predetermined number.

9. The apparatus of claim 8 , wherein the oscillator comprises a delay circuit, and the means for enabling the oscillator comprises means for coupling an output of the delay circuit to an input of the delay circuit.

10. The apparatus of claim 9 , wherein the means for coupling the output of the delay circuit to the input of the delay circuit comprises means for coupling the output of the delay circuit to the output of the delay circuit through an inverter.

11. The apparatus of claim 9 , wherein the delay circuit comprises a plurality of delay elements coupled in series.

12. The apparatus of claim 9 , wherein the means for disabling the oscillator comprises means for blocking the output of the delay circuit from the input of the delay circuit.

13. A delay device, comprising:
an oscillator; and
a count circuit having an input and an output, wherein the count circuit is configured to enable the oscillator in response to receiving a first rising edge at the input, to count a number of oscillations of the oscillator, to output a second rising edge at the output if the number of oscillations reaches a predetermined number, and to disable the oscillator until a third rising edge is received at the input in response to the number of oscillations reaching the predetermined number.

14. The delay device of claim 13 , wherein the oscillator comprises:
a delay circuit having an input and an output;
an oscillation enable/disable circuit configured to selectively enable and disable the oscillator based on a control signal from the count circuit, wherein the oscillation enable/disable circuit enables the oscillator by coupling the output of the delay circuit to the input of the delay circuit, and disables the oscillator by blocking the output of the delay circuit from the input of the delay circuit.

15. The delay device of claim 14 , wherein the delay circuit comprises a plurality of delay elements coupled in series.

16. The delay device of claim 15 , wherein the oscillation enable/disable circuit comprises a NAND gate having a first input coupled to the output of the delay circuit, a second input coupled to the count circuit for receiving the control signal, and an output coupled to the input of the delay circuit.

17. The delay circuit of claim 16 , wherein the plurality of delay elements comprises a plurality of NAND gates.

18. A delay device, comprising:
a first delay stage, the first delay stage comprising:
a first oscillator; and
a first count circuit having an input and an output, wherein the first count circuit is configured to transition the output of the first count circuit from a high logic state to a low logic state in response to receiving a first rising edge at the input of the first count circuit, to count a number of oscillations of the first oscillator in response to receiving a the first rising edge at the input of the first count circuit, and to output a second rising edge at the output of the first count circuit if the number of oscillations of the first oscillator reaches a first predetermined number; and

a second delay stage, the second delay stage comprising:
a second oscillator; and
a second count circuit having an input coupled to the output of the first count circuit and an output, wherein the second count circuit is configured to receive the transition from the high logic state to the low logic state at the input of the second count circuit, to count a number of oscillations of the second oscillator in response to receiving the second rising edge at the input of the second count circuit, and to output a third rising edge at the output of the second count circuit if the number of oscillations of the second oscillator reaches a second predetermined number.

19. The delay device of claim 18 , wherein the first count circuit is configured to enable the first oscillator in response to receiving the first rising edge, and to disable the first oscillator in response to the number of oscillations of the first oscillator reaching the first predetermined number.

20. The delay device of claim 19 , wherein the second count circuit is configured to enable the second oscillator in response to receiving the second rising edge, and to disable the second oscillator in response to the number of oscillations of the second oscillator reaching the second predetermined number.

21. The delay device of claim 20 , wherein the first and second predetermined numbers are the same.

22. The delay device of claim 19 , wherein the first oscillator comprises:
a delay circuit having an input and an output;
an oscillation enable/disable circuit configured to selectively enable and disable the first oscillator based on a control signal from the first count circuit, wherein the oscillation enable/disable circuit enables the first oscillator by coupling the output of the delay circuit to the input of the delay circuit, and disables the first oscillator by blocking the output of the delay circuit from the input of the delay circuit.

23. The delay device of claim 18 , further comprising:
a timing circuit configured to output the first rising edge to the first delay stage and to output a fourth rising edge, wherein the fourth rising edge is delayed with respect to the first rising edge by approximately one period of a reference clock;
a phase frequency det

Assignees

• Qualcomm Inc

Inventors

• Diffenderfer Jan Christian
• Cheng Yuehchun Claire

Classifications

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• H03K2005/00286

  Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency · CPC title

• H03K2005/00247

  using counters · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title