Tunable capacitor integrated on one semiconductor die or on one module

Patent metadata

Field	Value
Publication number	US-9520854-B2
Application number	US-201314013235-A
Country	US
Kind code	B2
Filing date	Aug 29, 2013
Priority date	Apr 3, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Disclosed is a tunable capacitor. The tunable capacitor according to a first embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L. The tunable capacitor according to a second embodiment of the present invention includes: a first capacitor; and a switching transistor which switches on/off the connection of the first capacitor between the first terminal and the second terminal, wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module.

First claim

What is claimed is:

1. A tunable capacitor comprising:
a first capacitor;
a switching transistor which switches on/off a connection of the first capacitor between a first terminal and a second terminal; and
a converter configured to convert a signal applied to a gate terminal G of the switching transistor and apply the converted signal to a drain terminal D and a source terminal S of the switching transistor,
wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L.

2. The tunable capacitor of claim 1 , wherein when the switching transistor is in an on-state, a high signal H is applied to the gate terminal G, and a low signal L is applied to a body terminal B, the drain terminal D and the source terminal S, and wherein when the switching transistor is in an off-state, the low signal L is applied to the gate terminal G and the body terminal B, and the high signal H is applied to the drain terminal D and the source terminal S.

3. The tunable capacitor of claim 1 , wherein the switching transistor is a stacked transistor formed by connecting in series a plurality of transistors.

4. The tunable capacitor of claim 1 , wherein the gate terminal G and a body terminal B of the switching transistor are connected in series to a resistance respectively.

5. The tunable capacitor of claim 1 , wherein the first capacitor is formed by connecting in series or in parallel a plurality of capacitors.

6. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 1 , wherein the plurality of the tunable capacitors are connected in parallel to each other.

7. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 1 , wherein the plurality of the tunable capacitors are connected in parallel to each other.

8. The tunable capacitor array of claim 6 , wherein an equivalent capacitance of the plurality of the tunable capacitors is 2 m-1 ×C1 (here, m is a natural number less than or equal to n), wherein channel width-to-length ratios W/L of the switching transistors of the plurality of the tunable capacitors are 2 m-1 ×W1 (here, m is a natural number less than or equal to n) respectively, and wherein the n is a number of the tunable capacitors, wherein the C1 is an equivalent capacitance of a particular tunable capacitor, and wherein the W1 is a channel width-to-length ratio W/L of the switching transistor.

9. The tunable capacitor array of claim 6 , further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

10. The tunable capacitor array of claim 8 , further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

11. The tunable capacitor array of claim 6 , further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

12. The tunable capacitor array of claim 8 , further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

13. A tunable capacitor comprising:
a first capacitor;
a switching transistor which switches on/off a connection of the first capacitor between a first terminal and a second terminal; and
a converter configured to convert a signal applied to a gate terminal G of the switching transistor and apply the converted signal to a drain terminal D and a source terminal S of the switching transistor,
wherein an on/off operation of the switching transistor is performed by a high signal H and a low signal L, and wherein the tunable capacitor is integrated on one semiconductor die or on one module.

14. The tunable capacitor of claim 13 , wherein when the switching transistor is in an on-state, a high signal H is applied to the gate terminal G, and a low signal L is applied to a body terminal B, the drain terminal D and the source terminal S, and wherein when the switching transistor is in an off-state, the low signal L is applied to the gate terminal G and the body terminal B, and the high signal H is applied to the drain terminal D and the source terminal S.

15. The tunable capacitor of claim 13 , wherein the switching transistor is a stacked transistor formed by connecting in series a plurality of transistors.

16. The tunable capacitor of claim 13 , wherein the gate terminal G and a body terminal B of the switching transistor are connected in series to a resistance respectively.

17. The tunable capacitor of claim 13 , wherein the first capacitor is formed by connecting in series or in parallel a plurality of capacitors.

18. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 13 , wherein the plurality of the tunable capacitors are connected in parallel to each other.

19. A tunable capacitor array comprising a plurality of the tunable capacitors according to claim 13 , wherein the plurality of the tunable capacitors are connected in parallel to each other.

20. The tunable capacitor array of claim 18 , wherein an equivalent capacitance of the plurality of the tunable capacitors is 2 m-1 ×C1 (here, m is a natural number less than or equal to n), wherein channel width-to-length ratios W/L of the switching transistors of the plurality of the tunable capacitors are 2 m-1 ×W1 (here, m is a natural number less than or equal to n) respectively, and wherein the n is a number of the tunable capacitors, wherein the C1 is an equivalent capacitance of a particular tunable capacitor, and wherein the W1 is a channel width-to-length ratio W/L of the switching transistor.

21. The tunable capacitor array of claim 18 , further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

22. The tunable capacitor array of claim 20 , further comprising a fixed capacitor which is connected in parallel to a plurality of the tunable capacitors.

23. The tunable capacitor array of claim 18 , further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

24. The tunable capacitor array of claim 20 , further comprising a controller which receives a digital control signal and controls on/off of the switching transistor.

Assignees

• Hideep Inc
• Hideep Inc

Inventors

• Kim Bonkee
• Cho Youngho
• Im Donggu
• Kim Bumkyum

Classifications

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H03H7/38 Primary

  Impedance-matching networks · CPC title

• H03H11/28

  Impedance matching networks · CPC title