Ultraviolet light emitting device separated from growth substrate and method of fabricating the same

US9520533B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9520533-B2
Application numberUS-201514875578-A
CountryUS
Kind codeB2
Filing dateOct 5, 2015
Priority dateApr 5, 2013
Publication dateDec 13, 2016
Grant dateDec 13, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A UV light emitting device and a method for fabricating the same are disclosed. The method includes forming a first super-lattice layer including Al x Ga (1-x) N on a substrate, forming a sacrificial layer including Al z Ga (1-z) N on the first super-lattice layer, partially removing the sacrificial layer, forming an epitaxial layer on the sacrificial layer, and separating the substrate from the epitaxial layer, wherein the sacrificial layer includes voids, the substrate is separated from the epitaxial layer at the sacrificial layer, and forming an epitaxial layer includes forming an n-type semiconductor layer including n-type Al u Ga (1-u) N (0<u≦z≦x<1). With this structure, the light emitting device can emit UV light and be separated from the substrate.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of fabricating a UV light emitting device, comprising: forming a first super-lattice layer comprising Al x Ga (1-x) N on a substrate; forming a sacrificial layer comprising Al z Ga (1-z) N on the first super-lattice layer; partially removing the sacrificial layer; forming an epitaxial layer on the sacrificial layer; and separating the substrate from the epitaxial layer, wherein the sacrificial layer comprises voids, the substrate is separated from the epitaxial layer at the sacrificial layer, and wherein the forming of the epitaxial layer comprises forming an n-type semiconductor layer comprising n-type Al u Ga (1-u) N (0<u≦z≦x<1). 2. The method of claim 1 , wherein the forming of the n-type semiconductor layer comprises: forming a first n-type semiconductor layer on the sacrificial layer at a first temperature; forming a second n-type semiconductor layer on the first n-type semiconductor layer at a second temperature; and forming a third n-type semiconductor layer on the second n-type semiconductor layer at a third temperature, wherein the second temperature is different from the first temperature and the third temperature. 3. The method of claim 2 , wherein the first temperature is less than or equal to the third temperature, and the third temperature is less than the second temperature. 4. The method of claim 1 , further comprising: forming a second super-lattice layer comprising Al y Ga (1-y )N (0<u≦z≦y≦x<1) on the first super-lattice layer, before forming the sacrificial layer, wherein the x ranges from 0.75 to 0.85, the z ranges from 0.55 to 0.65, and the u ranges from 0.45 to 0.55. 5. The method of claim 1 , wherein the first super-lattice layer comprises a stack structure including AlN layers and Al x Ga (1-x) N layers alternately stacked one above another. 6. The method of claim 1 , further comprising: forming a buffer layer on the substrate, before forming the first super-lattice layer. 7. The method of claim 6 , wherein the buffer layer comprises AlN. 8. The method of claim 1 , wherein the sacrificial layer comprises an n-type impurity, and wherein the partially removing of the sacrificial layer comprises: forming a mask pattern on the sacrificial layer; and forming fine voids in the sacrificial layer through electrochemical etching of the sacrificial layer. 9. The method of claim 8 , wherein at least some of the fine voids are combined to form the voids in the sacrificial layer during the formation of the epitaxial layer. 10. The method of claim 8 , wherein the separating of the substrate from the epitaxial layer comprises chemically etching the mask pattern using an etching solution. 11. The method of claim 8 , wherein the separating of the substrate from the epitaxial layer comprises applying stress to the sacrificial layer. 12. The method of claim 1 , wherein the separating of the substrate from the epitaxial layer comprises applying stress to the sacrificial layer. 13. The method of claim 1 , further comprising: forming a secondary substrate on the epitaxial layer, before separating the substrate from the epitaxial layer. 14. The method of claim 13 , further comprising: dividing the epitaxial layer and the secondary substrate, from which the substrate is separated, into a plurality of areas. 15. A template for fabrication of a UV light emitting device, comprising: a substrate; a first super-lattice layer disposed on the substrate and comprising Al x Ga (1-x) N; and a sacrificial layer disposed on the first super-lattice layer and comprising Al z Ga (1-z) N (0<z≦x<1); wherein the sacrificial layer comprises an n-type impurity having a concentration of 3×10 18 /cm 3 to 3×10 19 /cm 3 . 16. The template of claim 15 , further comprising: a second super-lattice layer disposed between the first super-lattice layer and the sacrificial layer and comprising Al y Ga (1-y) N (0≦z≦y≦x<1). 17. The template of claim 15 , further comprising: an AlN buffer layer disposed between the substrate and the first super-lattice layer.

Assignees

Inventors

Classifications

  • Nitrides · CPC title

  • Alternating layers, e.g. superlattice · CPC title

  • Nitrides · CPC title

  • Lateral overgrowth · CPC title

  • characterised by the preparation of substrate for selective deposition · CPC title

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What does patent US9520533B2 cover?
A UV light emitting device and a method for fabricating the same are disclosed. The method includes forming a first super-lattice layer including Al x Ga (1-x) N on a substrate, forming a sacrificial layer including Al z Ga (1-z) N on the first super-lattice layer, partially removing the sacrificial layer, forming an epitaxial layer on the sacrificial layer, and separating the substrate from th…
Who is the assignee on this patent?
Seoul Viosys Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/3216. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).