Vertical gate-all-around field effect transistors and methods of forming same

Patent metadata

Field	Value
Publication number	US-9520466-B2
Application number	US-201514659262-A
Country	US
Kind code	B2
Filing date	Mar 16, 2015
Priority date	Mar 16, 2015
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A plurality of nanowires is formed in the recess. A gate stack is formed over the substrate, the gate stack surrounding the plurality of nanowires.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a template layer on a substrate, the template layer having a first recess therein;
forming a plurality of first nanowires in the first recess; and
forming a first gate stack, the first gate stack surrounding the plurality of first nanowires.

2. The method of claim 1 , further comprising:
forming a plurality of second nanowires in a second recess of the template layer, a width of the second recess being different from a width of the first recess, a number of the plurality of second nanowires being different from a number of the plurality of first nanowires; and
forming a second gate stack, the second gate stack surrounding the plurality of second nanowires.

3. The method of claim 1 , further comprising:
forming a plurality of second nanowires in a second recess of the template layer, a width of the plurality of second nanowires being different from a width of the plurality of first nanowires; and
forming a second gate stack, the second gate stack surrounding the plurality of second nanowires.

4. The method of claim 1 , wherein the template layer comprises a dielectric material, and wherein the first recess exposes a portion of the substrate.

5. The method of claim 4 , further comprising:
doping the portion of the substrate to form a first source/drain feature; and
doping portions of the plurality of first nanowires to form a second source/drain feature.

6. The method of claim 1 , wherein the template layer comprises a conductive oxide material, and wherein a bottom of the first recess is disposed in the template layer.

7. The method of claim 6 , further comprising doping portions of the plurality of first nanowires to form a first source/drain feature, wherein a portion of the template layer disposed below the plurality of first nanowires forms a second source/drain feature.

8. A method of forming a semiconductor device, the method comprising:
forming a template layer on a substrate;
patterning the template layer to form a first recess and a second recess in the template layer, a width of the first recess being different from the a width of the second recess;
epitaxially growing a plurality of first nanowires in the first recess and a plurality of second nanowires in the second recess;
forming a first gate stack, the first gate stack surrounding the plurality of first nanowires; and
forming a second gate stack, the second gate stack surrounding the plurality of second nanowires.

9. The method of claim 8 , wherein a number of the plurality of second nanowires is different from a number of the plurality of first nanowires.

10. The method of claim 8 , wherein a width of the plurality of second nanowires is different from a width of the plurality of first nanowires.

11. The method of claim 8 , wherein the plurality of first nanowires comprises a III-V compound semiconductor material.

12. The method of claim 8 , wherein the plurality of first nanowires and the plurality of second nanowires are epitaxially grown using a selective-area metal-organic chemical vapor deposition (MOCVD) method.

13. The method of claim 8 , wherein the template layer comprises a conductive oxide material, and wherein at least a portion of the template layer is interposed between the substrate and the plurality of first nanowires.

14. The method of claim 8 , wherein the template layer comprises a dielectric material, and wherein the plurality of first nanowires contacts the substrate.

15. A method of forming a semiconductor device, the method comprising:
doping a substrate to form a first source/drain region in the substrate;
forming a template layer over the first source/drain region;
etching the template layer to form a first opening in the template layer, the first opening exposing the first source/drain region;
epitaxially growing a plurality of nanowires in the first opening;
depositing a gate dielectric layer over the substrate, the gate dielectric layer surrounding the plurality of nanowires; and
depositing a gate electrode layer over the substrate, the gate electrode layer surrounding the gate dielectric layer.

16. The method of claim 15 , further comprising:
depositing a first dielectric layer over the substrate, the first dielectric layer surrounding the gate electrode layer;
recessing the gate dielectric layer, the gate electrode layer and the first dielectric layer to expose portions of the plurality of nanowires; and
doping the portions of the plurality of nanowires to form a second source/drain region.

17. The method of claim 16 , further comprising forming a second dielectric layer over the first dielectric layer, at least a portion of the second dielectric layer surrounding the second source/drain region.

18. The method of claim 17 , further comprising etching the first dielectric layer and the second dielectric layer to form a second opening, a third opening and a fourth opening, the second opening extending through the second dielectric layer, the first dielectric layer, the gate dielectric layer, the template layer and exposing the first source/drain region, the third opening extending through the second dielectric layer and exposing the second source/drain region, the fourth opening extending through the second dielectric layer, the first dielectric layer and exposing the gate electrode layer.

19. The method of claim 18 , further comprising filling the second opening, the third opening and the fourth opening with a conductive material to form a first conductive plug in the second opening, a second conductive plug in the third opening and a third conductive plug in the fourth opening.

20. The method of claim 15 , further comprising etching the gate electrode layer to expose at least a portion of the gate dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Holland Martin Christopher
• Duriez Blandine
• Van Dal Mark

Classifications

• H10P14/3466

  Crystal orientation · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title