Floating body memory cell having gates favoring different conductivity type regions

Patent metadata

Field	Value
Publication number	US-9520399-B2
Application number	US-201615209622-A
Country	US
Kind code	B2
Filing date	Jul 13, 2016
Priority date	Dec 22, 2006
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate comprising a P well region having a first semiconductor fin protruding therefrom and an N well region having a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin, wherein the P well region is directly adjacent to the N well region in the semiconductor substrate;
a trench isolation layer disposed on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer;
a gate dielectric layer disposed on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins;
an n type metal gate layer disposed over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, wherein the n type metal gate layer is further disposed on a portion of but not all of the trench isolation layer; and
a p type metal gate layer disposed over the gate dielectric layer over the second semiconductor fin, wherein the p type metal gate layer is further disposed over the trench isolation layer and over the n type metal gate layer.

2. The semiconductor structure of claim 1 , wherein the p type metal gate layer comprises titanium nitride.

3. The semiconductor structure of claim 1 , wherein the n type metal gate layer comprises titanium.

4. The semiconductor structure of claim 1 , wherein the p type metal gate layer has a work function in the range of 4.6 to 5.2 eV.

5. The semiconductor structure of claim 1 , wherein the n type metal gate layer has a work function in the range of 3.9 to 4.6 eV.

6. The semiconductor structure of claim 1 , wherein the gate dielectric layer comprises HfO 2 .

7. The semiconductor structure of claim 1 , wherein the p type metal gate layer comprises titanium nitride, the n type metal gate layer comprises titanium, and the gate dielectric layer comprises HfO 2 .

8. The semiconductor structure of claim 1 , wherein the semiconductor substrate is a bulk silicon semiconductor substrate.

9. A method of fabricating a semiconductor structure, the method comprising:
forming a P well region and an N well region in a semiconductor substrate, wherein the P well region is directly adjacent to the N well region;
forming a first semiconductor fin in the P well region and forming a second semiconductor fin in the N well region, the first semiconductor fin spaced apart from the second semiconductor fin;
forming a trench isolation layer on the semiconductor substrate between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer;
forming a gate dielectric layer on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins;
forming an n type metal layer over the gate dielectric layer;
patterning the n type metal layer to form an n type metal gate layer over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, wherein the n type metal gate layer is further formed on a portion of but not all of the trench isolation layer; and
forming a p type metal gate layer over the gate dielectric layer over the second semiconductor fin, wherein the p type metal gate layer is further formed over the trench isolation layer and over the n type metal gate layer.

10. The method of claim 9 , wherein the p type metal gate layer comprises titanium nitride.

11. The method of claim 9 , wherein the n type metal gate layer comprises titanium.

12. The method of claim 9 , wherein the p type metal gate layer has a work function in the range of 4.6 to 5.2 eV.

13. The method of claim 9 , wherein the n type metal gate layer has a work function in the range of 3.9 to 4.6 eV.

14. The method of claim 9 , wherein the gate dielectric layer comprises HfO 2 .

15. The method of claim 9 , wherein the p type metal gate layer comprises titanium nitride, the n type metal gate layer comprises titanium, and the gate dielectric layer comprises HfO 2 .

16. The method of claim 9 , wherein the semiconductor substrate is a bulk silicon semiconductor substrate.

Assignees

• Chang Peter L D
• Avci Uygar E
• Kencke David
• Ban Ibrahim
• Intel Corp

Inventors

• Chang Peter L D
• Avci Uygar E
• Kencke David
• Ban Ibrahim

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• Y10S257/903

  FET configuration adapted for use as static memory cell · CPC title

• H10D86/201 Primary

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D84/859

  comprising both N-type and P-type wells, e.g. twin-tub · CPC title