Method of fabricating an integrated circuit (IC) package having a plurality of spaced apart pad portion

US9520306B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9520306-B2
Application numberUS-201213618509-A
CountryUS
Kind codeB2
Filing dateSep 14, 2012
Priority dateJun 10, 1998
Publication dateDec 13, 2016
Grant dateDec 13, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first surface of the leadframe strip, including the semiconductor die and wire bonds, is encapsulated in a molding material such that at least one surface of the leadframe strip is exposed. The integrated circuit package is singulated from a remainder of the leadframe strip.

First claim

Opening claim text (preview).

What is claimed is: 1. A process for fabricating an integrated circuit package, comprising: providing a leadframe strip having an upper surface and a lower surface; applying an etch-resist mask to the upper and lower surfaces; patterning the etch-resist mask to expose portions of the upper and lower surfaces; selectively etching both the upper and lower surfaces of the leadframe strip by completely etching through portions of the leadframe strip to define a die attach pad and a plurality of contact pads, and only partially etching through portions of the leadframe strip to form a plurality of spaced apart pad portions on the lower surface; mounting a semiconductor die to said die attach pad; wire bonding said semiconductor die to respective ones of said contact pads; encapsulating the upper surface of said leadframe strip, said semiconductor die, and wire bonds in a molding material, the lower surface of said leadframe strip being exposed; and singulating said integrated circuit package from a remainder of said leadframe strip. 2. The process according to claim 1 , wherein said selectively etching comprises selectively etching such that said plurality of pad portions are shaped and oriented to inhibit entrapment of air during encapsulation. 3. The process according to claim 1 , wherein said selectively etching comprises selectively etching said leadframe strip to define a continuous portion on a first side of the die attach pad and said plurality of pad portions extending from the continuous portion to a second side of the die attach pad. 4. The process according to claim 3 , wherein mounting said semiconductor die comprises mounting said semiconductor die to said first side of the die attach pad. 5. The process according to claim 4 , wherein said selectively etching comprises selectively etching to provide said plurality of pad portions wherein each of said pad portions have a generally square cross-section. 6. The process according to claim 4 , wherein said selectively etching comprises selectively etching to provide said plurality of pad portions wherein each of said pad portions have a generally circular cross-section. 7. The process according to claim 5 , wherein said selectively etching comprises selectively etching to provide said pad portions in a diamond pattern such that sides of said pad portions form an oblique angle with sides of said molding material. 8. The process according to claim 1 , wherein the pad portions form an array. 9. The process according to claim 1 , wherein said selectively etching comprises selectively etching to provide said die attach pad such that each of said plurality of pad portions have a generally square cross-section. 10. The process according to claim 1 , wherein said selectively etching comprises selectively etching to provide said die attach pad such that each of said plurality of pad portions have a generally circular cross-section. 11. The process according to claim 9 , wherein said selectively etching comprises selectively etching to provide said pad portions in a diamond pattern in which sides of said pad portions are at an oblique angle with sides of said molding material. 12. The process according to claim 1 , further comprising applying solder paste to the plurality of contact pads and to said at least one side of said die attach pad.

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What does patent US9520306B2 cover?
A process for fabricating an integrated circuit package includes selectively etching a leadframe strip to define a die attach pad and a plurality of contact pads. At least one side of the die attach pad has a plurality of spaced apart pad portions. A semiconductor die is mounted to the die attach pad and wires are bonded from the semiconductor die to respective ones of the contact pads. A first…
Who is the assignee on this patent?
Lin Geraldine Tsui Yee, De Munnik Walter, Kwan Kin Pui, and 5 more
What technology area does this patent fall under?
Primary CPC classification H10W74/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).