Semiconductor device having stacked oxide semiconductor layers

US9520287B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9520287-B2
Application numberUS-201414296893-A
CountryUS
Kind codeB2
Filing dateJun 5, 2014
Priority dateNov 28, 2009
Publication dateDec 13, 2016
Grant dateDec 13, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a gate electrode; a gate insulating film over the gate electrode; a first oxide semiconductor layer over the gate insulating film; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the second oxide semiconductor layer, wherein the second oxide semiconductor layer comprises a channel formation region which overlaps with the gate electrode with the first oxide semiconductor layer and the gate insulating film interposed therebetween, and wherein the second oxide semiconductor layer comprises crystals which are c-axis-aligned. 2. The semiconductor device according to claim 1 , further comprising: an insulating film over and in contact with the third oxide semiconductor layer; and a conductive layer over the insulating film, wherein the gate electrode and the conductive layer overlap with each other with the channel formation region interposed therebetween. 3. The semiconductor device according to claim 1 , wherein the first oxide semiconductor layer comprises an amorphous region. 4. The semiconductor device according to claim 1 , wherein the third oxide semiconductor layer comprises crystals which are c-axis-aligned. 5. The semiconductor device according to claim 1 , wherein the c-axes of the crystals in the second oxide semiconductor layer are aligned perpendicular to a surface of the second oxide semiconductor layer. 6. The semiconductor device according to claim 1 , wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer contains indium and zinc. 7. A semiconductor device comprising: a gate electrode; a gate insulating film; a first oxide semiconductor layer; a second oxide semiconductor layer; a third oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the second oxide semiconductor layer, wherein the second oxide semiconductor layer is between the first oxide semiconductor layer and the third oxide semiconductor layer, wherein the second oxide semiconductor layer comprises a channel formation region, wherein the gate electrode and the channel formation region overlap with each other with the first oxide semiconductor layer and the gate insulating film interposed therebetween, and wherein the second oxide semiconductor layer comprises crystals which are c-axis-aligned. 8. The semiconductor device according to claim 7 , wherein the first oxide semiconductor layer comprises an amorphous region. 9. The semiconductor device according to claim 7 , wherein the third oxide semiconductor layer comprises crystals which are c-axis-aligned. 10. The semiconductor device according to claim 7 , wherein the c-axes of the crystals in the second oxide semiconductor layer are aligned perpendicular to a surface of the second oxide semiconductor layer. 11. The semiconductor device according to claim 7 , wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer contains indium, gallium and zinc, and wherein composition ratio of the second oxide semiconductor layer and the third oxide semiconductor layer are different from each other. 12. The semiconductor device according to claim 7 , wherein a material of the second oxide semiconductor layer and a material of the third oxide semiconductor layer are different from each other. 13. A semiconductor device comprising: a gate electrode; a gate insulating film; an oxide semiconductor layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer; and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, wherein a relation of E c −E f <E g /2 is satisfied where E c is an energy at a bottom of a conduction band of the oxide semiconductor layer, E f is a Fermi energy of the oxide semiconductor layer, and E g is a band gap of the oxide semiconductor layer, wherein the second oxide semiconductor layer comprises a channel formation region, wherein the channel formation region and the gate electrode overlap with each other with the gate insulating film and the first oxide semiconductor layer interposed therebetween, and wherein the second oxide semiconductor layer comprises crystals which are c-axis-aligned. 14. The semiconductor device according to claim 13 , further comprising: an insulating film over and in contact with the third oxide semiconductor layer; and a conductive layer over the insulating film, wherein the gate electrode and the conductive layer overlap with each other with the channel formation region interposed therebetween. 15. The semiconductor device according to claim 13 , wherein the first oxide semiconductor layer comprises an amorphous region. 16. The semiconductor device according to claim 13 , wherein the third oxide semiconductor layer comprises crystals which are c-axis-aligned. 17. The semiconductor device according to claim 13 , wherein each of the second oxide semiconductor layer and the third oxide semiconductor layer contains indium, gallium and zinc, and wherein composition ratio of the second oxide semiconductor layer and the third oxide semiconductor layer are different from each other. 18. The semiconductor device according to claim 13 , wherein a material of the second oxide semiconductor layer and a material of the third oxide semiconductor layer are different from each other.

Assignees

Inventors

Classifications

  • Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

  • Amorphous · CPC title

  • consisting of two layers · CPC title

  • being crystalline insulating materials · CPC title

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9520287B2 cover?
One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component ov…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10P14/2921. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).