Wiring board and method for manufacturing wiring board

Patent metadata

Field	Value
Publication number	US-9520222-B2
Application number	US-201314041638-A
Country	US
Kind code	B2
Filing date	Sep 30, 2013
Priority date	Sep 28, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A wiring board includes a substrate including first insulation layers, a second insulation layer on the first layers, a third insulation layer on the second layer, and a plain conductor on the third layer. The substrate has inductor forming portion in which inductor patterns are formed on the first layers and first via conductors formed in the first layers such that the first via conductors connect the inductor patterns through the first layers, the substrate has a land on the second layer and a second via conductor in the second layer such that the second via conductor connects the land and the outermost inductor pattern, the substrate has a third via conductor in the third layer such that the third via conductor connects the plain conductor and land and has the central axis passing through the center of the third via conductor inside projected region of the second via conductor.

First claim

What is claimed is:

1. A wiring board, comprising:
a substrate comprising a plurality of first insulation layers, a plurality of second insulation layers formed on the outermost first insulation layers of the first insulation layers, respectively, a plurality of third insulation layers formed on the second insulation layers, respectively, and a plurality of plain conductors formed on the third insulation layers, respectively,
wherein the substrate has an inductor forming portion in which a plurality of inductor patterns is formed on the plurality of first insulation layers, respectively, and a plurality of first via conductors formed in the first insulation layers, respectively, such that the first via conductors are connecting the inductor patterns through the first insulation layers, the substrate has a plurality of land structures formed on the second insulation layers, respectively, and a plurality of second via conductors formed in the second insulation layers, respectively, such that the plurality of second via conductors is connecting the land structures and the outermost inductor patterns of the inductor patterns, respectively, the substrate has a plurality of third via conductors formed in the third insulation layers, respectively, such that the plurality of third via conductors is connecting the plain conductors and the land structures, respectively, and each has a central axis passing through the center of each of the third via conductors inside a projected region of a respective one of the second via conductors and that the plurality of outermost inductor patterns of the inductor patterns is formed in the substrate such that the outermost inductor patterns are separated 100 μm or more from the plain conductors, respectively.

2. The wiring board according to claim 1 , wherein each of the land structures has a thickness which is less than a thickness of each of the inductor patterns.

3. The wiring board according to claim 1 , wherein the substrate has no other conductor between the outermost inductor patterns of the inductor patterns and the plain conductors except the second via conductors, the third via conductors and the land portions.

4. The wiring board according to claim 1 , wherein each of the first insulation layers, second insulation layers and third insulation layers has an inorganic fiber reinforcing material.

5. The wiring board according to claim 1 , wherein each of the plain conductors has a plurality of mesh holes.

6. The wiring board according to claim 1 , further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern, wherein the fourth insulation layer does not contain an inorganic fiber reinforcing material.

7. The wiring board according to claim 6 , wherein each of the inductor patterns has a thickness which is greater than a thickness of the conductive pattern.

8. The wiring board according to claim 1 , wherein each of the inductor patterns comprises a metal foil formed on a respective layer of the first insulation layers, an electroless plated film on the metal foil, and an electrolytic plated film on the electroless plated film.

9. The wiring board according to claim 1 , further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern.

10. The wiring board according to claim 9 , wherein the inductor pattern has a thickness which is greater than a thickness of the conductive pattern.

11. The wiring board according to claim 1 , wherein each of the land structures has a thickness which is less than a thickness of each of the inductor patterns, and each of the inductor patterns comprises a metal foil formed on a respective layer of the first insulation layers, an electroless plated film on the metal foil, and an electrolytic plated film on the electroless plated film.

12. The wiring board according to claim 1 , further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern, wherein the fourth insulation layer does not contain an inorganic fiber reinforcing material, and each of the first insulation layers, second insulation layers and third insulation layers has an inorganic fiber reinforcing material.

13. The wiring board according to claim 12 , wherein each of the inductor patterns has a thickness which is greater than a thickness of the conductive pattern.

14. The wiring board according to claim 1 , further comprising a buildup layer comprising a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern, wherein the fourth insulation layer does not contain an inorganic fiber reinforcing material, and the respective one of the plain conductors has a plurality of mesh holes.

15. The wiring board according to claim 1 , further comprising:
a buildup layer formed on the substrate and configured to mount a semiconductor electronic component such that the semiconductor electronic component is positioned directly over the inductor forming portion of the substrate.

16. The wiring board according to claim 1 , further comprising:
a buildup layer formed on the substrate and configured to mount a semiconductor electronic component such that the semiconductor electronic component is positioned directly over the inductor forming portion of the substrate,
wherein the buildup layer comprises a conductive pattern formed on one of the third insulation layers and a respective one of the plain conductors and a fourth insulation layer laminated on the conductive pattern.

Assignees

• Ibiden Co Ltd

Inventors

• Tominaga Ryojiro
• Ino Keinosuke

Classifications

• Y10T156/10

  Methods of surface bonding and/or assembly therefor · CPC title

• H05K2201/0191

  wherein the thickness of the dielectric plays an important role · CPC title

• H01F41/005

  Impregnating or encapsulating (insulating of windings H01F41/12) · CPC title

• H05K1/165

  incorporating printed inductors · CPC title

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title