Semiconductor memory device including three-dimensional memory cell array structure and operating method thereof

Patent metadata

Field	Value
Publication number	US-9520198-B2
Application number	US-201414570813-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Jul 25, 2014
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

An operating method includes biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines; floating the channel regions of the unselected cell strings; increasing the first pass voltage to a second pass voltage during the floating of the channel regions; and reading data from selected memory cells of selected cell strings among the cell strings.

First claim

What is claimed is:

1. An operating method of a three-dimensional semiconductor memory device including cell strings each having memory cells stacked over a substrate and coupled to a plurality of word lines, the operating method comprising:
biasing channel regions of unselected cell strings among the cell strings to an initial voltage while applying a first pass voltage to the plurality of word lines;
floating the channel regions of the unselected cell strings;
increasing the…

Assignees

• Sk Hynix Inc

Inventors

• Choi Se Kyoung
• Choi Eun Seok
• Oh Jung Seok

Classifications

• G11C16/24 Primary

  Physics · mapped topic

• G11C7/14

  Physics · mapped topic

• G11C16/3427

  Physics · mapped topic

• G11C16/08

  Physics · mapped topic