Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-9520188-B2
Application number	US-201514931124-A
Country	US
Kind code	B2
Filing date	Nov 3, 2015
Priority date	Mar 24, 2011
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.

First claim

The invention claimed is:

1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cell layers in a first direction, one of the memory cell layers having a plurality of first lines, a plurality of second lines intersecting the first lines, and a plurality of memory cells provided at intersections of the first lines and the second lines and operative to store data in accordance with different resistance states; and
an access circuit operative to access to the memory cells via the first lines and the second lines,
one of the memory cells changing a resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity opposite in polarity to the first polarity,
the access circuit operative to, during accessing to selected one of the memory cells,
set a first voltage to the first lines and the second lines,
then set a second voltage higher than the first voltage to the first lines and the second lines,
then set a third voltage higher than the second voltage to a first line or a second line connected to the selected memory cell, set the first voltage to the other one, and bring at least one of a first line and a second line connected to non-selected one of the memory cells into a state in which certain potential is not supplied/applied from external,

certain one of the memory cell layers sharing the first lines with another memory cell layer located adjacent to the certain memory cell layer on one side in the first direction, and sharing the second lines with another memory cell layer located adjacent thereto on the other side,
the access circuit including a sense amplifier operative to sense a cell current flowing in the selected memory cell via the first line, and a driver operative to supply a voltage, required for access to the selected memory cell, to the second line, and
the driver shared among second lines disposed at odd-numbered/even-numbered orders counted in the first direction, of second lines disposed on the same position in the memory cell layers.

2. The semiconductor memory device according to claim 1 , wherein
a voltage-current characteristic of the memory cell at the first polarity has a larger gradient when the memory cell is in the second resistance state than that in the first resistance state, and
the voltage-current characteristic of the memory cell at the second polarity has substantially the same gradient when the memory cell is in the first resistance state as that in the second resistance state.

3. The semiconductor memory device according to claim 1 , wherein
the access circuit is operative to, when a defective portion exists in the memory cell array, execute address management to an access inhibited area containing the defective portion, and access to memory cells outside the access inhibited area under the address management.

4. The semiconductor memory device according to claim 1 , wherein
the access circuit is operative to select one from the first lines and maintain the selected first line to the third voltage, sequentially switch and select one from the second lines, set the first voltage to the selected second lines, and bring other second lines into the state in which the certain potential is not supplied/applied from external to sequentially access to memory cells provided at the intersections of the selected first line and the selected second lines.

5. The semiconductor memory device according to claim 1 , wherein
the access circuit is operative to select one from the first lines and maintain the selected first line to the third voltage, sequentially switch and select one from the second lines, set the first voltage to the selected second lines, and bring other second lines into the state in which the certain potential is not supplied/applied from external to sequentially access to memory cells provided at the intersections of the selected first line and the selected second lines.

6. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cell layers in a first direction, one of the memory cell layers having a plurality of first lines, a plurality of second lines intersecting the first lines, and a plurality of memory cells provided at intersections of the first lines and the second lines and operative to store data in accordance with different resistance states; and
an access circuit operative to access to the memory cells via the first lines and the second lines,
one of the memory cells changing a resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity opposite in polarity to the first polarity,
the access circuit operative to, during accessing to selected one of the memory cells,
set a first voltage to the first lines and the second lines,
then set a second voltage higher than the first voltage to the first lines and the second lines,
then set a third voltage higher than the second voltage to a first line or a second line connected to the selected memory cell, set the first voltage to the other one, and bring at least one of a first line and a second line connected to non-selected one of the memory cells into a state in which certain potential is not supplied/applied from external, and

the access circuit including a line position selector circuit operative to select a position of the first line or the second line disposed in one of the memory cell layers, and a memory cell layer selector circuit operative to select the memory cell layer.

7. The semiconductor memory device according to claim 6 , wherein
a voltage-current characteristic of the memory cell at the first polarity has a larger gradient when the memory cell is in the second resistance state than that in the first resistance state, and
the voltage-current characteristic of the memory cell at the second polarity has substantially the same gradient when the memory cell is in the first resistance state as that in the second resistance state.

8. The semiconductor memory device according to claim 6 , wherein
the access circuit is operative to, when a defective portion exists in the memory cell array, execute address management to an access inhibited area containing the defective portion, and access to memory cells outside the access inhibited area under the address management.

9. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cell layers in a first direction, one of the memory cell layers having a plurality of first lines, a plurality of second lines intersecting the first lines, and a plurality of memory cells provided at intersections of the first lines and the second lines and operative to store data in accordance with different resistance states; and
an access circuit operative to access to the memory cells via the first lines and the second lines,
one of the memory cells changing a resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity opposite in polarity to the first polarity,
the access circuit operative to, during accessing to selected one of the memory cells,
set a first voltage to the first lines and the second lines,
then set a second voltage higher than t

Assignees

• Toshiba Kk

Inventors

• Toda Haruki

Classifications

• G11C13/003 Primary

  Cell access · CPC title

• G11C13/0023 Primary

  Address circuits or decoders · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C2213/71

  Three dimensional array · CPC title