Memory apparatus, systems, and methods
US-2015325309-A1 · Nov 12, 2015 · US
US9520183B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9520183-B2 |
| Application number | US-201514707684-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 8, 2015 |
| Priority date | Aug 26, 2011 |
| Publication date | Dec 13, 2016 |
| Grant date | Dec 13, 2016 |
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Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation.
Opening claim text (preview).
The invention claimed is: 1. A method of operating a memory, comprising: providing an analog ramp signal to a control gate of a memory cell; converting a value of a digital signal corresponding to the analog ramp signal to a converted digital value; and providing the converted digital value to a buffer coupled to the memory cell, wherein a difference between the converted digital value and the digital signal value results in a difference in threshold voltage in the memory cell…
Physics · mapped topic
Physics · mapped topic
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