Nano-electro-mechanical based memory
US-9224448-B2 · Dec 29, 2015 · US
Memory elements with relay devices
US9520182B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9520182-B2 |
| Application number | US-201314092298-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 27, 2013 |
| Priority date | Nov 23, 2011 |
| Publication date | Dec 13, 2016 |
| Grant date | Dec 13, 2016 |
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Abstract
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Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory element, comprising: a first inverting circuit that includes at least a pair of transistors with channels that are formed in a first layer; and a second inverting circuit that is coupled to the first inverting circuit and that includes a transistor with a channel that is formed in a second layer above the first layer, wherein the pair of transistor in the first inverting circuit is formed in a substrate in the first layer, and wherein the transist…
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Physics · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- G11C11/52Primary
Physics · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9520182B2 cover?
- Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be inte…
- Who is the assignee on this patent?
- Altera Corp
- What technology area does this patent fall under?
- Primary CPC classification G11C11/52. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).