Architecture and instructions for accessing multi-dimensional formatted surface memory

US9519947B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9519947-B2
Application numberUS-89017110-A
CountryUS
Kind codeB2
Filing dateSep 24, 2010
Priority dateSep 25, 2009
Publication dateDec 13, 2016
Grant dateDec 13, 2016

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Abstract

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One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.

First claim

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What is claimed is: 1. A method for accessing multi-dimensional formatted surface memory by a program, comprising: receiving a surface instruction that specifies an x-coordinate of a sample and a y-coordinate of the sample, wherein the sample is associated with a multi-dimensional formatted surface; computing an address of a location in the multi-dimensional formatted surface memory based on the x-coordinate, the y-coordinate, and attributes of the multi-dimensional formatted su…

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What does patent US9519947B2 cover?
One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce…
Who is the assignee on this patent?
Nickolls John R, Fahs Brian, Nyland Lars, and 3 more
What technology area does this patent fall under?
Primary CPC classification G06T1/60. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 13 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).