Multiprocessor system with independent direct access to bulk solid state memory resources

Patent metadata

Field	Value
Publication number	US-9519615-B2
Application number	US-201414249289-A
Country	US
Kind code	B2
Filing date	Apr 9, 2014
Priority date	Apr 9, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A system includes a collection of central processing units, where each central processing unit is connected to at least one other central processing unit and a root path into at least 10 Tera Bytes of solid state memory resources. Each central processing unit directly accesses solid state memory resources without swapping solid state memory contents into main memory.

First claim

What is claimed is:

1. A system, comprising:
a collection of central processing units, wherein each central processing unit is connected to at least one other central processing unit and a root path into solid state memory resources, wherein each central processing unit directly accesses the solid state memory resources without swapping solid state memory contents into a main memory; and
a collection of root processors connected to the collection of central processing units, the collection of root processors configured to organize the solid state memory resources into resource pools, maintain an erasure count for each resource pool, and execute a generational garbage collector protocol in which an assigned generation of a resource pool is periodically altered based upon the erasure count for the resource pool.

2. The system of claim 1 wherein each central processing unit independently accesses the solid state memory resources without interfering with an access by another central processing unit.

3. The system of claim 1 wherein the root path includes at least one root with a memory interface and a branch interface, wherein the branch interface provides an interface to individual leaf interface controllers, wherein the branch interface is configured with computational resources to coordinate data search in individual solid state memory leaves and data processing of retrieved data from the individual solid state memory leaves as a part of the solid state memory resources.

4. The system of claim 3 wherein each individual leaf interface controller is configured with computational resources to search for data within individual solid state memory leaves and data processing of retrieved data from the individual solid state memory leaves.

5. The system of claim 1 wherein the collection of central processing units is configured for directly accessing the solid state memory resources through a hierarchy of root controllers and branch controllers, wherein the root controllers and branch controllers are configured to selectively move data between individual root controllers and individual branch controllers without supervision from any of the central processing units.

6. The system of claim 5 wherein each individual leaf interface controller independently moves data between corresponding solid state memory leaves in response to a request from a root controller or a branch controller.

7. A system of claim 1 wherein the collection of central processing units is configured for directly accessing the solid state memory resources through a hierarchy of root controllers and branch controllers configured for chained data reads that exploit parallelism associated with the solid state memory resources.

8. The system of claim 7 wherein the root controllers utilize branch connections to individual leaves to distribute a chain of read requests so that each individual read is directed to a different leaf.

9. The system of claim 1 wherein the collection of central processing units is configured for directly accessing the solid state memory resources through a hierarchy of root controllers and branch controllers configured for distributed data writes to the solid state memory resources to facilitate parallelism in subsequent data reads from the solid state memory resources.

10. The system of claim 7 wherein the branch controllers distribute a chain of read requests so that each read is directed to a different leaf.

11. The system of claim 1 wherein the collection of root processors is configured to utilize the assigned generation of the resource pool to balance traffic across communication channels to the solid state memory resources.

12. The system of claim 1 further comprising a moving window forward error correcting code accumulator configured to incrementally add arriving data symbols to previously accumulated data correction codes and remove a previously accumulated data correction code.

13. The system of claim 1 wherein the collection of central processing units is configured for directly accessing the solid state memory resources by determining that a primary host of a data segment is unavailable and retrieving the data segment from a redundant host.

14. The system of claim 13 wherein the data segment is reconstructed by one of the central processing units from data protection codes retrieved from the redundant host.

15. The system of claim 13 wherein the data segment is reconstructed by a root processor from data protection codes retrieved from the redundant host.

16. The system of claim 13 wherein the data segment is reconstructed by a branch processor from data protection codes retrieved from the redundant host.

17. The system of claim 13 wherein the data segment is reconstructed by a leaf processor from data protection codes retrieved from the redundant host.

18. A system of claim 1 wherein central processing units of the collection are configured to:
issue a read command to internal memory resources, request data from the solid state memory resources, receive from the solid state memory resources a command of allocated resources within the internal memory resources, and fill the data in the allocated resources.

19. A system of claim 1 wherein the collection of central processing units is configured for directly accessing the solid state memory resources through a hierarchy of branch controllers and leaf controllers configured to correct small bit errors in hardware, wherein the central processing units are configured to execute software to correct large bit errors.

Assignees

• Emc Corp

Inventors

• Carlson Jr Frederic Roy
• Himelstein Mark
• Wilford Bruce
• Arai Dan
• Emberson David R

Classifications

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F1/00

  Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76) · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F16/2246

  Trees, e.g. B+trees · CPC title

• G06F15/167 Primary

  using a common memory, e.g. mailbox · CPC title