Error recovery following speculative execution with an instruction processing pipeline

Patent metadata

Field	Value
Publication number	US-9519538-B2
Application number	US-201113067510-A
Country	US
Kind code	B2
Filing date	Jun 6, 2011
Priority date	Apr 3, 2007
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.

First claim

We claim:

1. Apparatus for processing data comprising:
an instruction processing pipeline having a plurality of pipeline stages;
at least one error detector, coupled to a pipeline stage of said instruction processing pipeline and responsive to at least one signal value within said pipeline stage, configured to detect a processing error associated with an erring program instruction within said pipeline stage;
error recovery circuitry, coupled to said at least one error detector and responsive to detection of a processing error by said error detector, configured to initiate an error recovery operation, wherein said pipeline stage, includes a first main storage element and a second main storage element, configured to sample a signal for respective program instructions at respective operational sampling points in an alternating sequence, and said error recovery operation includes replacing an incorrect signal value stored in one of said first main storage element and said second main storage element with a correct value subsequent to said operational sampling point while a signal value for a following program instruction remains stored in the other of said first main storage element and said second main storage element; and
thread control circuitry, coupled to said instruction processing pipeline and responsive to program instructions from a plurality of different program threads to control supply of an interleaved stream of program instructions from different program threads, configured to store signal values from a first program thread in said first main storage element, and signal values from a second different program thread in said second main storage element,
wherein a thread identifying signal accompanies a program instruction passing along said instruction processing pipeline and is coupled to said first main storage element and said second main storage element to gate sampling thereby of said signal at said operational sampling point.

2. Apparatus as claimed in claim 1 , wherein said error detector includes a shared shadow storage element for sampling said signal value subsequent to said operational sampling point and a comparator for detecting any difference between values detected by an alternating one of said first main storage element and said second main storage element and said shared shadow storage element, a difference being indicative of said processing error.

3. Apparatus as claimed in claim 2 , wherein a value sampled by said shared shadow storage element is used to replace an erroneous value with said main storage element as part of said error recovery operation.

4. Apparatus for processing data comprising:
means for processing program instructions having a plurality of pipeline stages;
means, coupled to a pipeline stage of said means for processing program instructions and responsive to at least one signal value within said pipeline stage, for detecting a processing error associated with an erring program instruction within said pipeline stage;
means, coupled to said means for detecting a processing error and responsive to detection of a processing error by said means for detecting a processing error, for initiating an error recovery operation, wherein
said pipeline stage includes a first main storage element means and a second main storage element means for sampling a signal for respective program instructions at respective operational sampling points in an alternating sequence, said error recovery operation includes replacing an incorrect signal value stored in one of said first main storage element means and said second main storage element means with a correct value subsequent to said operational sampling point while a signal value for a following program instruction remains stored in an other of said first main storage element means and said second main storage element means; and
means for controlling supply of program instructions, said means for controlling coupled to said means for processing program instructions and responsive to program instructions from a plurality of different program threads to control supply of an interleaved stream of program instructions from different program threads, said means for processing program instructions storing signal values from a first program thread in said first main storage element means, and signal values from a second different program thread being stored in said second main storage element means,
wherein a thread identifying signal accompanies a program instruction passing along said instruction processing pipeline and is coupled to said first main storage element and said second main storage element to gate sampling thereby of said signal at said operational sampling point.

5. A method for processing data comprising:
processing program instructions in an instruction processing pipeline having a plurality of pipeline stages;
in response to at least one signal value within a pipeline stage of said instruction processing pipeline, detecting a processing error associated with an erring program instruction within said pipeline stage;
in response to detection of a processing error, initiating an error recovery operation;
sampling a signal with a pipeline stage for respective program instructions at respective operational sampling points in an alternating sequence using a first main storage element and a second main storage element; and
replacing an incorrect signal value stored in one of said first main storage element and said second main storage element with a correct value subsequent to said operational sampling point while a signal value for a following program instruction remains stored in the other of said first main storage element and said second main storage element, supplying an interleaved stream of program instructions from different program threads to said instruction processing pipeline, signal values from a first program thread in said first main storage element, and signal values from a second different program thread in said second main storage element,
wherein a thread identifying signal accompanies a program instruction passing along said instruction processing pipeline and is coupled to said first main storage element and said second main storage element to gate sampling thereby of said signal at said operational sampling point.

6. A method as claimed in claim 5 , comprising sampling using a shared shadow storage element said signal value subsequent to said operational sampling point and detecting any difference between values detected by an alternating one of said first main storage element and said second main storage element and said shared shadow storage element, a difference being indicative of said processing error.

7. A method as claimed in claim 6 , wherein a value sampled by said shared shadow storage element is used to replace an erroneous value with said main storage element as part of said error recovery operation.

Assignees

• Özer Emre
• Das Shidhartha
• Bull David Michael
• Advanced Risc Mach Ltd

Inventors

• Özer Emre
• Das Shidhartha
• Bull David Michael

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3863

  using multiple copies of the architectural state, e.g. shadow registers · CPC title

• G06F9/3842 Primary

  Speculative instruction execution · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title