Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator
US-2016328234-A1 · Nov 10, 2016 · US
US9519488B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9519488-B2 |
| Application number | US-201213398305-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 16, 2012 |
| Priority date | Jul 25, 2011 |
| Publication date | Dec 13, 2016 |
| Grant date | Dec 13, 2016 |
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An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.
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What is claimed is: 1. A processor, comprising: a core comprising of functional units; an intrinsic module disposed outside the core; and an interface module to perform relaying between the intrinsic module and a functional unit among the functional units, such that stall cycle hiding is performed in response to a stall occurring in the core or the intrinsic module, and wherein whether the stall cycle hiding is performed by an output FIFO register or an input FIFO register is…
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