Display panel including a trench defined in a substrate

Patent metadata

Field	Value
Publication number	US-9519173-B2
Application number	US-201213604242-A
Country	US
Kind code	B2
Filing date	Sep 5, 2012
Priority date	Mar 21, 2012
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A display panel includes a base substrate, a common electrode, a liquid crystal layer, a pixel electrode, a gate line, a data line, a switching element, a color filter and a light blocking pattern. The base substrate includes a trench. The common electrode is disposed in the trench. The liquid crystal layer is disposed in the trench and disposed on the common electrode. The pixel electrode is disposed on the base substrate and the liquid crystal layer. The gate line, the data line and the switching element are disposed on the base substrate and the pixel electrode. The color filter and the light blocking pattern are disposed on the gate line, the data line and the switching element.

First claim

What is claimed is:

1. A display panel comprising:
a base substrate comprising a bottom portion which extends to define walls of the base substrate, wherein
the bottom portion and the walls of the base substrate define a trench in the base substrate, and
a distal end of the walls which opposes the bottom portion defines an upper surface of the trench;

a common electrode in the trench;
a liquid crystal layer on the common electrode and completely in the trench defined in the base substrate;
a filter layer in which a color filter and a light blocking pattern are alternated, the filter layer facing the upper surface of the trench in which the liquid crystal layer is disposed on the common electrode;
a pixel electrode disposed between the color filter and the light blocking pattern of the filter layer and the upper surface of the trench;
a first passivation layer between the liquid crystal layer and the pixel electrode;
a thin film transistor array comprising a gate line, a data line and a switching element, the thin film transistor array disposed between the color filter and the light blocking pattern of the filter layer and the pixel electrode; and
a second passivation layer disposed between the pixel electrode and the thin film transistor array, wherein the switching element includes a drain electrode that passes through the second passivation layer to be connected to the pixel electrode.

2. The display panel of claim 1 , further comprising:
a third passivation layer between the switching element and the light blocking pattern.

3. The display panel of claim 2 , wherein the switching element comprises:
a gate electrode on the second passivation layer;
a gate insulating layer on the gate electrode;
a semiconductor layer on the gate insulating layer and overlapping the gate electrode; and
a source electrode on the semiconductor layer and overlapping the semiconductor layer.

4. The display panel of claim 3 , wherein
the second passivation layer and the gate insulating layer include a contact hole, and
the drain electrode passes through the contact holes to be connected to the pixel electrode.

5. The display panel of claim 1 , further comprising
a display area corresponding to the color filter, and a peripheral area corresponding to the light blocking pattern, and
an injection hole in the peripheral area, extending from an outside of the trench to an inside of the trench and through the pixel electrode, and through which the liquid crystal layer is provided to the trench.

6. The display panel of claim 5 , further comprising a hole light blocking pattern in the trench, in a different layer than the light blocking pattern, and corresponding to the injection hole.

7. The display panel of claim 1 , further comprising a planarizing layer on the color filter and the light blocking pattern, wherein the planarizing layer compensates a height difference between the color filter and the light blocking pattern.

8. The display panel of claim 7 , further comprising a first polarizing plate under the base substrate and a second polarizing plate on the planarizing layer.

Assignees

• Jung Yang-Ho
• Shim Seung-Bo
• Ju Jin-Ho
• Kim Jun-Gi
• Samsung Display Co Ltd

Inventors

• Jung Yang-Ho
• Shim Seung-Bo
• Ju Jin-Ho
• Kim Jun-Gi

Classifications

• G02F2001/13685

  Physics · mapped topic

• G02F1/1341

  Filling or closing of cells · CPC title

• G02F1/1337

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

• G02F2001/134318

  Physics · mapped topic

• G02F2001/136222

  Physics · mapped topic