Tunable silicon grating couplers

Patent metadata

Field	Value
Publication number	US-9519163-B2
Application number	US-201314034950-A
Country	US
Kind code	B2
Filing date	Sep 24, 2013
Priority date	Sep 24, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

A photonic integrated circuit (PIC) is described. This PIC includes a grating coupler for surface-normal coupling that has an alternating pattern of grating teeth and grating trenches, where the grating trenches are filled with an electro-optical material. By applying an electric potential to the grating teeth, the index of refraction of the electro-optical material can be modified.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a buried-oxide layer disposed on the substrate;
a semiconductor layer, disposed on the buried-oxide layer, having a top surface; and
a grating coupler, disposed in the semiconductor layer, having an alternating pattern of grating trenches and grating teeth adjacent to the grating trenches, wherein the grating coupler is a portion of the semiconductor layer, and wherein the grating trenches extend all the way through the semiconductor layer from the top surface to the buried-oxide layer;
wherein the grating trenches are filled with an electro-optical material; and
wherein the grating teeth are configured as electrodes to apply an electric potential across the electro-optical material to modify an index of refraction of the electro-optical material.

2. The integrated circuit of claim 1 , wherein the modification to the index of refraction changes one of: an operating wavelength of the grating coupler, a position alignment criterion of the grating coupler, and an angular alignment criterion of the grating coupler.

3. The integrated circuit of claim 1 , wherein the semiconductor layer under the grating teeth includes one of: an n-type dopant and a p-type dopant.

4. The integrated circuit of claim 1 , wherein the semiconductor layer under the grating teeth includes a p-type dopant and an n-type dopant; and
wherein the p-type dopant is included under alternating grating teeth and the n-type dopant is included under grating teeth interposed between the alternating grating teeth.

5. The integrated circuit of claim 4 , wherein the electric potential reverse biases pn-junctions in the semiconductor layer to deplete carriers.

6. The integrated circuit of claim 1 , wherein the grating trenches are etched from the top surface to the buried-oxide layer.

7. The integrated circuit of claim 1 , wherein the substrate, the buried-oxide layer and the semiconductor layer comprise a silicon-on-insulator technology.

8. The integrated circuit of claim 1 , wherein the semiconductor layer includes silicon.

9. A system, comprising an integrated circuit, wherein the integrated circuit includes:
a substrate;
a buried-oxide layer disposed on the substrate;
a semiconductor layer, disposed on the buried-oxide layer, having a top surface; and
a grating coupler, disposed in the semiconductor layer, having an alternating pattern of grating trenches and grating teeth adjacent to the grating trenches, wherein the grating coupler is a portion of the semiconductor layer, and wherein the grating trenches extend all the way through the semiconductor layer from the top surface to the buried-oxide layer;
wherein the grating trenches are filled with an electro-optical material; and
wherein the grating teeth are configured as electrodes to apply an electric potential across the electro-optical material to modify an index of refraction of the electro-optical material.

10. The system of claim 9 , wherein the modification to the index of refraction changes one of: an operating wavelength of the grating coupler, a position alignment criterion of the grating coupler, and an angular alignment criterion of the grating coupler.

11. The system of claim 9 , wherein the semiconductor layer under the grating teeth includes one of: an n-type dopant and a p-type dopant.

12. The system of claim 9 , wherein the semiconductor layer under the grating teeth includes a p-type dopant and an n-type dopant; and
wherein the p-type dopant is included under alternating grating teeth and the n-type dopant is included under grating teeth interposed between the alternating grating teeth.

13. The system of claim 12 , wherein the electric potential reverse biases pn-junctions in the semiconductor layer to deplete carriers.

14. The system of claim 9 , wherein the grating trenches are etched from the top surface to the buried-oxide layer.

15. The system of claim 9 , wherein the substrate, the buried-oxide layer and the semiconductor layer comprise a silicon-on-insulator technology.

16. The system of claim 9 , wherein the semiconductor layer includes silicon.

Assignees

• Oracle Int Corp

Inventors

• Zheng Xuezhe
• Yao Jin
• Li Guoliang
• Luo Ying L
• Cunningham John E
• Krishnamoorthy Ashok V

Classifications

• G02F2201/302

  grating coupler · CPC title

• G02F1/025 Primary

  in an optical waveguide structure (G02F1/017, {G02F1/2257} take precedence) · CPC title

• G02B6/24

  Coupling light guides · CPC title

• G02F2001/0154

  Physics · mapped topic

• G02B6/124

  Geodesic lenses or integrated gratings · CPC title