Offset and decision feedback equalization calibration

Patent metadata

Field	Value
Publication number	US-9515856-B2
Application number	US-201514720518-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	Sep 12, 2011
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

First claim

What is claimed is:

1. A receiver circuit, comprising:
a first sampling circuit configured to sample during a first calibration period, a first repeating bit position within a first signal pattern based on a first equalization parameter, the first repeating bit position having varying values over multiple transmission periods in the first signal pattern according to a known data pattern, the first signal pattern having a second repeating bit position of fixed latency relative to the first repeating bit position, the second repeating bit position in the first signal pattern having a first fixed logic value; and
an error comparator circuit configured to vary the first equalization parameter during the first calibration period while the first sampling circuit samples the first repeating bit position, to compare first resultant digital samples of the first repeating bit position with the known data pattern, and to set the first equalization parameter of the first sampling circuit in response to the comparing.

2. The receiver circuit of claim 1 , wherein the receiver circuit further comprises:
a second sampling circuit configured to sample the second repeating bit position; and
wherein the error comparator circuit is configured to selectively constrain an output of the second sampling circuit to either a first or second fixed sampler output value.

3. The receiver circuit of claim 2 , wherein the error comparator circuit is configured to set a reference voltage of the second sampling circuit to either a first reference level that is below a minimum signal level in the first signal pattern or to a second reference level that is above a maximum signal level in the first signal pattern.

4. The receiver circuit of claim 2 , wherein the first sampling circuit comprises:
a first comparator configured to sample the first repeating bit position when the output of the second sampling circuit is constrained to output the first fixed sampler output value; and
a second comparator configured to sample the first repeating bit position when the output of the second sampling circuit is constrained to output the second fixed sampler output value.

5. The receiver circuit of claim 4 , wherein the first sampling circuit further comprises:
a multiplexer configured to select an output of the first comparator when the output of the second sampling circuit is constrained to output the first fixed sampler output value and to select an output of the second comparator when the output of the second sampling circuit is constrained to output the second fixed sampler output value.

6. The receiver circuit of claim 1 ,
wherein the first sampling circuit is further configured to sample during a second calibration period, the first repeating bit position within a second signal pattern based on a second equalization parameter, the first repeating bit position having varying values over multiple transmission periods in the second signal pattern according to the known data pattern, the second signal pattern having the second repeating bit position of fixed latency relative to the first repeating bit position, the second repeating bit position in the second signal pattern having a second fixed logic value; and
wherein the error comparator is further configured to vary the second equalization parameter during the second calibration period while the first sampling circuit samples the first repeating bit position, to compare second resultant digital samples of the first repeating bit position with the known data pattern, and to set the second equalization parameter of the first sampling circuit in response to the comparing.

7. The receiver circuit of claim 6 , further comprising:
a second sampling circuit configured to sample during a third calibration period, the second repeating bit position within a third signal pattern based on a third equalization parameter, the second repeating bit position having varying values over multiple transmission periods in the third signal pattern according to the known data pattern, the third signal pattern having the first repeating bit position of fixed latency relative to the second repeating bit position, the first repeating bit position in the third signal pattern having the first fixed logic value; and
wherein the error comparator is further configured to vary the third equalization parameter during the third calibration period while the second sampling circuit samples the second repeating bit position, to compare third resultant digital samples of the second repeating bit position with the known data pattern, and to set the third equalization parameter of the second sampling circuit in response to the comparing.

8. The receiver circuit of claim 7 ,
wherein the second sampling circuit is further configured to sample during a fourth calibration period, the second repeating bit position within a fourth signal pattern based on a fourth equalization parameter, the second repeating bit position having varying values over multiple transmission periods in the fourth signal pattern according to the known data pattern, the fourth signal pattern having the first repeating bit position of fixed latency relative to the second repeating bit position, the first repeating bit position in the fourth signal pattern having the second fixed logic value; and
wherein the error comparator is further configured to vary the fourth equalization parameter during the fourth calibration period while the second sampling circuit samples the second repeating bit position, to compare fourth resultant digital samples of the second repeating bit position with the known data pattern, and to set the fourth equalization parameter of the second sampling circuit in response to the comparing.

9. The receiver circuit of claim 1 , wherein the receiver circuit is embodied in a memory controller.

10. A method for calibrating a decision feedback equalizer, the method comprising:
during a first calibration period, sampling by a first sampling circuit while varying a first equalization parameter of the decision feedback equalizer, a first repeating bit position within a first signal pattern, the first repeating bit position having varying values over multiple transmission periods of the first signal pattern according to a known data pattern, the first signal pattern having a second repeating bit position of fixed latency relative to the first repeating bit position, the second repeating bit position in the first signal pattern having a first fixed logic value;
comparing first resultant digital samples of the first repeating bit position with the known data pattern; and
setting the first equalization parameter of the first sampling circuit in response to the comparing.

11. The method of claim 10 , further comprising:
sampling, by a second sampling circuit, the second repeating bit position; and
selectively constraining an output of the second sampling circuit to either a first or second fixed sampler output value.

12. The method of claim 11 , wherein constraining the output of the second sampling circuit comprises:
setting a reference voltage of the second sampling circuit to either a first reference level that is below a minimum signal level in the first signal pattern or to a second reference level that is above a maximum signal level in the first signal pattern.

13. The method of claim 11 , wherein sampling the first repeating bit position comprises:
sampling, by a first comparator, the first repeating bit position when the output of the second sampling circuit is constrained to output the first fixed sampler output value; and
sampling, by a second comparator, the first repeating bit positi

Assignees

• Rambus Inc

Inventors

• Kaviani Kambiz
• Amirkhany Amir
• Wei Jason Chia-Jen
• Abbasfar Aliazam

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03063 Primary

  using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps · CPC title

• H04L25/03885

  adaptive · CPC title

• H04B1/123

  using adaptive balancing or compensation means (adaptive filter circuits and algorithms H03H) · CPC title