Forward error correction architecture and implementation for power/space efficient transmission systems

Patent metadata

Field	Value
Publication number	US-9515683-B2
Application number	US-201414459000-A
Country	US
Kind code	B2
Filing date	Aug 13, 2014
Priority date	Aug 13, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A concatenated Forward Error Correction (FEC) code method, at an intermediate point, includes receiving, from an ingress point, a signal that is fully encoded with a concatenated FEC code, wherein the concatenated FEC code includes at least an inner code and an outer code; partially decoding the signal by decoding the inner code at the intermediate point; and transmitting the partially decoded signal towards an egress point where the partially decoded signal is fully decoded.

First claim

What is claimed is:

1. A concatenated Forward Error Correction (FEC) code method, implemented in electronic circuitry or a network element at an intermediate point associated with transmission of a signal, the method comprising:
receiving, from an ingress point, the signal that is fully encoded with a concatenated FEC code, wherein the concatenated FEC code has at least an inner code and an outer code;
partially decoding the signal by decoding the inner code at the intermediate point; and
transmitting the partially decoded signal towards an egress point where the partially decoded signal is fully decoded.

2. The concatenated FEC method of claim 1 , wherein the transmitting is performed without re-encoding of the signal.

3. The concatenated FEC method of claim 1 , wherein the egress point is configured to perform multiple passes to fully decode the partially decoded signal.

4. The concatenated FEC method of claim 1 , wherein the intermediate point is one of a plurality of intermediate points in sequence between the ingress point and the egress point, and each of the plurality of intermediate points is configured to partially decode the signal by decoding the inner code.

5. The concatenated FEC method of claim 1 , further comprising:
monitoring error counts based on the partial decoding.

6. The concatenated FEC method of claim 1 , wherein the signal is fully encoded, at the ingress point, by encoding with the outer code, interleaving, and encoding with the inner code, and
wherein the signal is fully decoded, at the egress point, by decoding the inner code, de-interleaving, and decoding the outer code.

7. The concatenated FEC method of claim 1 , wherein the method is performed in an optical network where the ingress point is an add network element, the intermediate point is an express network element performing optical-electrical-optical regeneration, and the egress point is a drop network element.

8. The concatenated FEC code method of claim 1 , wherein the inner code is decoded at the intermediate point and any additional intermediate points in sequence between the ingress point and the egress point and the outer code is decoded once at a client egress point.

9. A transmission system, comprising:
an express electronic circuit or network element with a partial decoder configured to receive a signal and to partially decode the signal by decoding an inner code, wherein the signal is fully encoded, by an ingress electronic circuit or network element, with a concatenated Forward Error Correction (FEC) code which includes the inner code and an outer code; and
one or more express electronic circuits or network elements in sequence between the ingress electronic circuit or network element and the egress electronic circuit or network element, wherein each of the one or more express electronic circuits or network elements is configured to partially decode the signal by decoding the inner code of the signal,
wherein the express electronic circuit or network element is configured to transmit the partially decoded signal towards an egress electronic circuit or network element with a full decoder configured to fully decode the signal.

10. The transmission system of claim 9 , wherein the express electronic circuit or network element is configured to retransmit the signal without re-encoding the signal.

11. The transmission system of claim 9 , wherein the express electronic circuit or network element is configured to monitor error counts based on the partial decode.

12. The transmission system of claim 9 , wherein the ingress electronic circuit or network element has a full encoder configured to fully encode the signal by encoding with the outer code, interleaving, and encoding with the inner code, and
wherein the egress electronic circuit or network element has a full decoder configured to fully decode the signal by decoding the inner code, de-interleaving, and decoding the outer code.

13. The transmission system of claim 9 , wherein the transmission system is an optical network with the express network element performing optical-electrical-optical regeneration.

14. The transmission system of claim 9 , wherein the inner code is decoded at each intermediate point in sequence between the ingress electronic circuit or network element and the egress electronic circuit or network element and the outer code is decoded once at the egress electronic circuit or network element.

15. An apparatus, comprising:
circuitry configured to receive a signal from a channel, wherein the signal is encoded with a concatenated Forward Error Correction (FEC) code with an inner code and an outer code;
circuitry configured to perform a partial decode of the signal; and
circuitry configured to retransmit the partially decoded signal without re-encoding the signal,
wherein the apparatus is located in an express network element in a transmission system, wherein the express network element performs optical-electrical-optical regeneration of the signal though only partially decoding the concatenated FEC code.

16. The apparatus of claim 15 , further comprising:
circuitry configured to monitor for errors based on the partial decode.

17. The apparatus of claim 15 , wherein the apparatus is any of an electronic circuit for data origination, electronic circuits for data regeneration and retransmission, and electrical interconnect lines.

Assignees

• Mateosky John P
• Frankel Michael Y
• Ciena Corp

Inventors

• Mateosky John P
• Frankel Michael Y

Classifications

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/2909 Primary

  Product codes · CPC title

• H04L1/0064

  Concatenated codes · CPC title

• H04L2001/0097

  Relays · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title