Circuit, semiconductor device, and clock tree

Patent metadata

Field	Value
Publication number	US-9515661-B2
Application number	US-201514705619-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	May 9, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state.

First claim

What is claimed is:

1. A clock tree comprising a plurality of inverter circuits comprising:
a plurality of levels comprising:
a first inverter circuit in at least one odd-numbered level; and
a second inverter circuit in at least one even-numbered level,

wherein a first power supply potential is input to a source of a p-channel transistor of the first inverter circuit,
wherein a second power supply potential is input to a source of an n-channel transistor of the first inverter circuit,
wherein the first power supply potential is input to a source of a p-channel transistor of the second inverter circuit,
wherein the second power supply potential is input to a source of an n-channel transistor of the second inverter circuit,
wherein the first power supply potential is higher than the second power supply potential,
wherein the input of the first power supply potential to the source of the p-channel transistor of the first inverter circuit can be blocked, and
wherein a semiconductor region in each of the n-channel transistors of the first inverter circuit and the second inverter circuit includes an oxide semiconductor layer.

2. A clock tree comprising a plurality of inverter circuits comprising:
a plurality of levels comprising:
a first inverter circuit in at least one odd-numbered level; and
a second inverter circuit in at least one even-numbered level,

wherein a first power supply potential is input to a source of a p-channel transistor of the first inverter circuit,
wherein a second power supply potential is input to a source of an n-channel transistor of the first inverter circuit,
wherein the first power supply potential is input to a source of a p-channel transistor of the second inverter circuit,
wherein the second power supply potential is input to a source of an n-channel transistor of the second inverter circuit,
wherein an electrical connection between a drain of the p-channel transistor of the first inverter circuit and an output node of the first inverter circuit can be blocked,
wherein the first power supply potential is higher than the second power supply potential, and
wherein a semiconductor region in each of the n-channel transistors of the first inverter circuit and the second inverter circuit includes an oxide semiconductor layer.

3. The clock tree according to claim 1 , wherein each of the oxide semiconductor layers of the n-channel transistor of the first inverter circuit and the n-channel transistor of the second inverter circuit comprises In and Zn.

4. The clock tree according to claim 2 , wherein each of the oxide semiconductor layers of the n-channel transistor of the first inverter circuit and the n-channel transistor of the second inverter circuit comprises In and Zn.

5. A clock tree comprising a plurality of inverter circuits comprising:
a first inverter circuit; and
a second inverter circuit,
wherein an output node of the first inverter circuit is electrically connected to an input node of the second inverter circuit,
wherein a first power supply potential is input to a source of a p-channel transistor of the first inverter circuit,
wherein a second power supply potential is input to a source of an n-channel transistor of the first inverter circuit,
wherein the first power supply potential is input to a source of a p-channel transistor of the second inverter circuit,
wherein the second power supply potential is input to a source of an n-channel transistor of the second inverter circuit,
wherein the first power supply potential is higher than the second power supply potential,
wherein the input of the first power supply potential to the source of the p-channel transistor of the first inverter circuit can be blocked, and
wherein a semiconductor region in each of the n-channel transistors of the first inverter circuit and the second inverter circuit includes an oxide semiconductor layer.

6. A clock tree comprising a plurality of inverter circuits comprising:
a first inverter circuit; and
a second inverter circuit,
wherein an output node of the first inverter circuit is electrically connected to an input node of the second inverter circuit,
wherein a first power supply potential is input to a source of a p-channel transistor of the first inverter circuit,
wherein a second power supply potential is input to a source of an n-channel transistor of the first inverter circuit,
wherein the first power supply potential is input to a source of a p-channel transistor of the second inverter circuit,
wherein the second power supply potential is input to a source of an n-channel transistor of the second inverter circuit,
wherein an electrical connection between a drain of the p-channel transistor of the first inverter circuit and the output node of the first inverter circuit can be blocked,
wherein the first power supply potential is higher than the second power supply potential, and
wherein a semiconductor region in each of the n-channel transistors of the first inverter circuit and the second inverter circuit includes an oxide semiconductor layer.

7. The clock tree according to claim 5 , wherein each of the oxide semiconductor layers of the n-channel transistor of the first inverter circuit and the n-channel transistor of the second inverter circuit comprises In and Zn.

8. The clock tree according to claim 6 , wherein each of the oxide semiconductor layers of the n-channel transistor of the first inverter circuit and the n-channel transistor of the second inverter circuit comprises In and Zn.

9. An electronic part comprising:
a circuit portion comprising the clock tree according to claim 1 ; and
a wire electrically connected to the circuit portion.

10. An electronic device comprising:
the electronic part according to claim 9 ; and
at least one of a microphone, a speaker, a display portion, and an operation key.

Assignees

• Semiconductor Energy Lab

Inventors

• Kato Kiyoshi

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title