Programmable resistive elements as variable tuning elements

Patent metadata

Field	Value
Publication number	US-9515635-B1
Application number	US-201514807157-A
Country	US
Kind code	B1
Filing date	Jul 23, 2015
Priority date	Jul 23, 2015
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

First claim

What is claimed is:

1. An integrated circuit comprising:
a reference signal generation circuit comprising:
a first resistor and a second resistor formed in at least one front end of line (FEOL) device level of the integrated circuit, wherein
the first resistor and the second resistor are coupled in series,

an output node between the first resistor and the second resistor, wherein a reference signal is generated at the output node, and
a programmable resistive element formed in at least one back end of line (BEOL) wiring level of the integrated circuit, wherein
the programmable resistive element is coupled in series with the second resistor, and
a non-volatile resistive state of the programmable resistive element is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

2. The integrated circuit of claim 1 , further comprising:
a program circuit coupled to the programmable resistive element, wherein the program circuit is configured to
adjust the non-volatile resistive state of the programmable resistive element to trim the reference signal.

3. The integrated circuit of claim 2 , wherein
the program circuit is further coupled to the output node and is further configured to measure a first reference signal at the output node, in response to a selection of a program mode, and
apply a selected program signal to the programmable resistive element to adjust the non-volatile resistive state to another one of the plurality of non-volatile resistive states, in response to a determination that the first reference signal is not within a target signal range.

4. The integrated circuit of claim 3 , wherein
the selected program signal is selected from a plurality of program signals that each have an associated magnitude, polarity, and duration,
each of the plurality of program signals corresponds to an adjustment from the non-volatile resistive state to another one of the plurality of non-volatile resistive states,
each of the plurality of program signals is associated with one of a plurality of signal ranges outside of the target signal range, and
the selected program signal is associated with one of the plurality of signal ranges within which the first reference signal falls.

5. The integrated circuit of claim 3 , wherein
the reference signal comprises a reference voltage,
a first program signal is configured to adjust the programmable resistive element to a higher non-volatile resistive state, in response to the first reference signal having a value that is less than the target signal range, and
a second program signal is configured to adjust the programmable resistive element to a lower non-volatile resistive state, in response to the first reference signal having a value that is greater than the target signal range.

6. The integrated circuit of claim 3 , wherein
the reference signal comprises a reference current,
a first program signal is configured to adjust the programmable resistive element to a lower non-volatile resistive state, in response to the first reference signal having a value that is less than the target signal range, and
a second program signal is configured to adjust the programmable resistive element to a higher non-volatile resistive state, in response to the first reference signal having a value that is greater than the target signal range.

7. The integrated circuit of claim 1 , wherein
the plurality of non-volatile resistive states comprises a logic high non-volatile resistive state and a logic low non-volatile resistive state.

8. The integrated circuit of claim 1 , further comprising:
a third resistor formed in at least one FEOL device level, wherein
the third resistor is coupled in parallel with the programmable resistive element, and
the third resistor comprises polysilicon.

9. The integrated circuit of claim 1 , wherein
the programmable resistive element comprises an array of programmable resistive sub-elements,
the array comprises a first dimension of M and a second dimension of N,
M and N each being integers of 1 or greater, and
one or more non-volatile resistive states of the programmable resistive sub-elements vary in response to the program signal applied to the programmable resistive element.

Assignees

• Freescale Semiconductor Inc

Inventors

• Sadd Michael A
• Roy Anirban

Classifications

• G11C29/28

  Dependent multiple arrays, e.g. multi-bit arrays · CPC title

• H03K19/00369

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title

• G11C29/021 Primary

  in voltage or current generators · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C29/50008

  of impedance · CPC title