Apparatus and methods for high voltage variable capacitor arrays with body-to-gate diodes

Patent metadata

Field	Value
Publication number	US-9515631-B2
Application number	US-201514705429-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	Dec 3, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

First claim

What is claimed is:

1. An integrated circuit comprising:
a variable capacitor array including at least three variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, wherein each of the at least three variable capacitor cells includes:
two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors comprises a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors comprises a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series; and
a plurality of diodes configured to control a plurality of body voltages of the two or more pairs of anti-series MOS capacitors of each of the at least three variable capacitor cells to increase a power handling capability of each of the at least three variable capacitor cells,
wherein the integrated circuit does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array.

2. The integrated circuit of claim 1 , wherein the plurality of diodes comprises:
a first diode including an anode electrically connected to a body of the first MOS capacitor of each of the at least three variable capacitor cells and a cathode electrically connected to a gate of the first MOS capacitor of each of the at least three variable capacitor cells;
a second diode including an anode electrically connected to a body of the second MOS capacitor of each of the at least three variable capacitor cells and a cathode electrically connected to a gate of the second MOS capacitor of each of the at least three variable capacitor cells;
a third diode including an anode electrically connected to a body of the third MOS capacitor of each of the at least three variable capacitor cells and a cathode electrically connected to a gate of the third MOS capacitor of each of the at least three variable capacitor cells; and
a fourth diode including an anode electrically connected to a body of the fourth MOS capacitor of each of the at least three variable capacitor cells and a cathode electrically connected to a gate of the fourth MOS capacitor of each of the at least three variable capacitor cells.

3. The integrated circuit of claim 2 , wherein a third pair of the two or more pairs of anti-series MOS capacitors of each of the at least three variable capacitor cells includes a fifth MOS capacitor and a sixth MOS capacitor electrically connected in anti-series, wherein the plurality of diodes further comprises:
a fifth diode including an anode electrically connected to a body of the fifth MOS capacitor and a cathode electrically connected to a gate of the fifth MOS capacitor; and
a sixth diode including an anode electrically connected to a body of the sixth MOS capacitor and a cathode electrically connected to a gate of the sixth MOS capacitor.

4. The integrated circuit of claim 1 , wherein the plurality of diodes comprise a plurality of p-n junction diodes.

5. The integrated circuit of claim 1 , further comprising two or more drift protection resistors configured to balance a DC operating point across the two or more pairs of anti-series MOS capacitors of each of the at least three variable capacitor cells, wherein the two or more drift protection resistors comprise a first drift protection resistor electrically connected in parallel with the first pair of anti-series MOS capacitors of each of the at least three variable capacitor cells and a second drift protection resistor electrically connected in parallel with the second pair of anti-series MOS capacitors of each of the at least three variable capacitor cells.

6. The integrated circuit of claim 1 , wherein each of the at least three variable capacitor cells comprises at least three pairs of anti-series MOS capacitors.

7. The integrated circuit of claim 1 , further comprising a bias voltage generation circuit configured to bias the at least three variable capacitor cells to control a capacitance of the variable capacitor array.

8. The integrated circuit of claim 7 , wherein the bias voltage generation circuit is configured to bias at least a first variable capacitor cell of the at least three variable capacitor cells with a first bias voltage, wherein the bias voltage generation circuit is configured to control the first bias voltage to a voltage level selected from a discrete number of two or more bias voltage levels.

9. The integrated circuit of claim 8 , wherein the first MOS capacitor of each of the at least three variable capacitor cells and the second MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a first intermediate node, wherein the third MOS capacitor of each of the at least three variable capacitor cells and the fourth MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a second intermediate node, wherein the at least a first variable capacitor cell further includes:
a first control biasing resistor electrically connected between the first bias voltage and the first intermediate node; and
a second control biasing resistor electrically connected between the first bias voltage and the second intermediate node.

10. The integrated circuit of claim 9 , wherein the at least a first variable capacitor cell further comprises a plurality of DC biasing resistors configured to bias the two or more pairs of anti-series MOS capacitors of each of the at least three variable capacitor cells with a reference voltage.

11. The integrated circuit of claim 1 , wherein a gate of the first MOS capacitor of each of the at least three variable capacitor cells is electrically connected to a gate of the second MOS capacitor of each of the at least three variable capacitor cells, and wherein a gate of the third MOS capacitor of each of the at least three variable capacitor cells is electrically connected to a gate of the fourth MOS capacitor of each of the at least three variable capacitor cells.

12. The integrated circuit of claim 1 , wherein a source and a drain of the first MOS capacitor of each of the at least three variable capacitor cells are electrically connected to a source and a drain of the second MOS capacitor of each of the at least three variable capacitor cells, and wherein a source and a drain of the third MOS capacitor of each of the at least three variable capacitor cells are electrically connected to a source and a drain of the fourth MOS capacitor of each of the at least three variable capacitor cells.

13. The integrated circuit of claim 1 , wherein the integrated circuit is formed using a silicon on insulator (SOI) substrate.

14. An apparatus comprising:
a radio frequency (RF) input;
an RF output;
at least three variable capacitor cells electrically connected in parallel between the RF input and the RF output, wherein each of the at least three variable capacitor cells includes:
two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors comprises a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors comprises a third MOS capacitor and a fourth MOS capacitor electrically conne

Assignees

• Tdk Corp

Inventors

• Madan Anuj
• Gupta Dev V
• Lai Zhiguo

Classifications

• H10D84/212

  of only capacitors · CPC title

• H03H7/0138

  Electrical filters or coupling circuits · CPC title

• H03H7/0153 Primary

  Electrical filters; Controlling thereof · CPC title

• H01L27/0805

  Electricity · mapped topic

• H03H11/04

  Frequency selective two-port networks · CPC title