Methods of manufacturing semiconductor devices using cavities to distribute conductive patterning residue

Patent metadata

Field	Value
Publication number	US-9515255-B2
Application number	US-201414522865-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Jan 6, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming conductive pillars on the substrate;
forming a conductive layer on the conductive pillars with an air gap disposed between the conductive layer and the substrate and between the conductive pillars;
and
patterning the conductive layer to remove a first portion of the conductive layer to expose the air gap and leave respective second portions of the conductive layer on respective ones of the conductive pillars.

2. The method of claim 1 , wherein forming the conductive layer is preceded by forming a sacrificial layer on the substrate between the conductive pillars and further comprising
forming the air gap by removing the sacrificial layer.

3. The method of claim 2 , further comprising forming a capping insulating layer between the conductive pillars before the formation of the sacrificial layer and wherein the capping insulating layer extends onto sidewalls of the conductive pillars.

4. The method of claim 2 , further comprising:
forming a mold insulating layer on the sacrificial layer, the mold insulating layer exposing top surfaces of the conducive pillars; and
leaving the mold insulating layer after the sacrificial layer is removed.

5. The method of claim 4 , wherein the mold insulating layer is formed of a material having an etch selectivity with respect to the sacrificial layer.

6. The method of claim 1 , further comprising:
forming contacts connecting the conductive pillars to the substrate; and
forming conductive pads between the conductive pillars and the contacts.

7. The method of claim 1 , wherein some of the conductive pillars are spaced apart from each other at a first distance and wherein others of the conductive pillars are spaced apart from each other at a second distance greater than the first distance.

8. The method of claim 1 , wherein forming the conductive layer comprises:
sequentially forming a first conductive layer, an insulating layer, and a second conductive layer.

9. The method of claim 8 , wherein the first and second conductive layers are ferromagnetic layers.

10. The method of claim 1 , wherein forming the conductive layer is preceded by:
forming conductive pillars on the substrate;
sequentially forming a sacrificial layer and a mold insulating layer between the conductive pillars; and
removing the sacrificial layer to form the air gap.

11. The method of claim 10 , wherein forming the mold insulating layer comprises forming first mold patterns on sidewalls of upper portions of the conductive pillars,
wherein at least a portion of the sacrificial layer is exposed by openings between the first mold patterns and wherein the sacrificial layer is removed through the openings between the first mold patterns.

12. The method of claim 11 , wherein the first mold patterns are formed by a spacer formation process.

13. The method of claim 11 , wherein forming the mold insulating layer further comprises forming second mold patterns filling the openings between the first mold patterns after the removal of the sacrificial layer.

14. The method of claim 13 , further comprising performing a planarization process to expose top surfaces of the conductive pillars after the formation of the second mold patterns.

15. The method of claim 11 , wherein forming the first mold patterns comprises:
forming a first mold layer on the sacrificial layer; and
forming a through-hole in the first mold layer to expose the sacrificial layer.

16. The method of claim 1 , wherein forming the air gap comprises: formation of the conductive layer is preceded by forming a mold insulating layer having poor step coverage such that a space between the conductive pillars is not filled.

17. A method of manufacturing a magnetic memory device, the method comprising:
forming contacts on a substrate;
forming conductive pillars on the contacts;
forming a sacrificial layer and a mold insulating layer between the conductive pillars;
selectively removing the sacrificial layer to form an air gap between the mold insulating layer and the substrate;
forming a magnetic tunnel junction layer on the mold insulating layer; and
patterning the magnetic tunnel junction layer to expose the air gap.

18. The method of claim 17 , wherein forming the mold insulating layer comprises forming first mold patterns on sidewalls of upper portions of the conductive pillars.

Assignees

• Park Jongchul
• Bae Byoungjae
• Kim Inho
• Kwon Shin
• Noh Eunsun
• Park Insun
• Lee Sangmin
• Samsung Electronics Co Ltd

Inventors

• Park Jongchul
• Bae Byoungjae
• Kim Inho
• Kwon Shin
• Noh Eunsun
• Park Insun
• Lee Sangmin

Classifications

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/228

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic