Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9515150-B2
Application number	US-201414308751-A
Country	US
Kind code	B2
Filing date	Jun 19, 2014
Priority date	Jul 23, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate including a first region and a second region that is different from the first region;
forming first source/drain regions in the first region;
forming second source/drain regions in the second region;
forming sacrificial patterns on the first source/drain regions in the first region;
performing an oxidation process to form first mask patterns on the first source/drain regions and second mask patterns on the second source/drain regions;
wherein the second mask patterns have an etch selectivity with respect to the first mask patterns,
wherein portions of the sacrificial patterns are oxidized to form the first mask patterns, and
wherein top surfaces of the second source/drain are oxidized to form the second mask patterns during the oxidation process,
the method further comprising:
selectively removing the first mask patterns;
forming the first patterns on the first source/drain regions in the first region;
removing the second mask patterns after forming the first patterns; and
forming second patterns on the second source/drain regions in the second region,
wherein the first patterns include a first element and the second patterns include a second element that is different from the first element,
wherein the first patterns are ohmic patterns that contact the first source/drain regions,
wherein the second patterns are ohmic patterns that contact the second source/drain regions,
wherein forming the first pattern comprises:
removing residual portions of the sacrificial patterns that are not oxidized to expose the first source/drain regions;
forming a first metal layer on the exposed first source/drain regions:
reacting the first metal layer with the first source/drain regions; and
removing an unreacted portion of the first metal layer that does not react with the first source/drain regions.

2. The method of claim 1 , wherein the sacrificial patterns include germanium (Ge).

3. The method of claim 1 , wherein the first mask patterns include germanium oxide, and wherein the second mask patterns include silicon oxide.

4. The method of claim 1 , wherein forming the second patterns on the second source/drain regions comprises:
forming a second metal layer on the second source/drain regions exposed by removing the second mask patterns;
reacting the second metal layer with the second source/drain regions; and
removing an unreacted portion of the second metal layer that does not react with the second source/drain regions.

5. The method of claim 1 , further comprising:
forming first contact plugs that are electrically connected to the first source/drain regions, wherein the first patterns are arranged between the first contact plugs and the first source/drain regions; and
forming second contact plugs that are electrically connected to the second source/drain regions, wherein the second patterns are arranged between the second contact plugs and the second source/drain regions.

6. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate including a first region and a second region that is different from the first region;
forming first mask patterns on first source/drain regions in the first region;
forming, on second source/drain regions in the second region, second mask patterns having an etch selectivity with respect to the first mask patterns, while forming the first mask patterns;
selectively removing the first mask patterns;
forming first patterns on the first source/drain regions in the first region;
removing the second mask patterns after forming the first patterns; and
forming second patterns on the second source/drain regions in the second region,
wherein the first patterns are ohmic patterns that contact the first source/drain regions,
wherein the second patterns are ohmic patterns that contact the second source/drain regions,
wherein forming the first mask patterns comprises forming sacrificial patterns on the first source/drain regions,
wherein portions of the sacrificial patterns are oxidized to form the first mask patterns,
wherein forming the first patterns comprises:
removing residual portions of the sacrificial patterns that are not oxidized to expose the first source/drain regions;
forming a metal layer on the exposed first source/drain regions;
reacting the metal layer with the first source/drain regions; and
removing an unreacted portion of the metal layer that does not react with the first source/drain regions.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Xiong Junjie
• Cha Dongho
• Kang Myung Jin
• Do Kihoon

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/667 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title