Inductor device and fabrication method

Patent metadata

Field	Value
Publication number	US-9515133-B2
Application number	US-201414539896-A
Country	US
Kind code	B2
Filing date	Nov 12, 2014
Priority date	Jan 26, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate including a front-end device, the front-end device having a transistor, a first interlayer dielectric layer on the semiconductor substrate, and a metal plug in the first interlayer dielectric layer;
forming a second interlayer dielectric layer on the front-end device;
forming a metal layer in the second interlayer dielectric layer, the metal layer comprising an interconnect member connected to the metal plug and a virtual interconnect member;
removing the virtual interconnect member to form a trench;
filling the trench with a dielectric filling layer;
forming an intermetallic dielectric layer on the second interlayer dielectric layer; and
forming an inductor on the intermetallic dielectric layer.

2. The method of claim 1 , wherein filling the trench comprises:
performing a chemical mechanical polishing process to remove excess of the dielectric filling layer.

3. The method of claim 2 , wherein the chemical mechanical polishing process stops when a surface of the barrier layer is exposed.

4. The method of claim 1 , wherein filling the trench comprises a chemical vapor deposition process.

5. The method of claim 1 , wherein removing the virtual interconnect member comprises:
forming a barrier layer on the second interlayer dielectric layer;
forming a mask layer on the barrier layer having an opening over the virtual interconnect member;
removing a portion of the barrier layer exposed by the opening to expose the virtual interconnect member;
removing the exposed virtual interconnect member; and
removing the mask layer.

6. The method of claim 5 , wherein the mask layer is a patterned photoresist.

7. The method of claim 5 , wherein removing the portion of the barrier layer comprises a dry etching process, and removing the exposed virtual interconnect member comprises a wet etching process.

8. The method of claim 1 , wherein the dielectric filler layer and the second interlayer dielectric layer are formed of a same material.

9. The method of claim 1 , wherein the dielectric filling layer comprises silicon oxide.

10. The method of claim 1 , wherein forming the metal layer in the second interlayer dielectric layer comprises:
forming a plurality of trenches in second interlayer dielectric layer;
forming a metal layer in the trenches;
planarizing the metal layer by performing a chemical mechanical polishing process.

11. The method of claim 1 , wherein the inductor comprises a projection in a direction vertical to the intermetallic dielectric layer covering the dielectric filling layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Huang Herb He
• Ge Hongtao
• Li Haiting

Classifications

• H10P95/064

  the removal being chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title