Thin film transistor array panel and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9515093-B2
Application number	US-201414466317-A
Country	US
Kind code	B2
Filing date	Aug 22, 2014
Priority date	Jan 10, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.

First claim

What is claimed is:

1. A thin film transistor array panel comprising:
a substrate;
a gate electrode disposed on the substrate;
a semiconductor layer disposed on the substrate;
a gate insulating layer disposed between the gate electrode and the semiconductor layer;
a source electrode disposed on a first side of the semiconductor layer, wherein the source electrode includes a first lateral surface;
a drain electrode disposed on a second side of the semiconductor layer, wherein the drain electrode includes a second lateral surface and is spaced apart from the source electrode, wherein the first and second lateral surfaces define a spacing which overlaps the gate electrode;
a metal silicide layer being in direct contact with the first and second lateral surfaces; and
a passivation layer disposed on the metal silicide layer, the source electrode and the drain electrode.

2. The thin film transistor array panel of claim 1 ,
wherein the semiconductor layer is in contact with the passivation layer through the spacing defined by the first lateral surface of the source electrode and the second lateral surface of the second electrode.

3. The thin film transistor array panel of claim 2 , further comprising a data line connected to the source electrode,
wherein a top surface of the data line is lower than a top surface of the source electrode,
wherein the source electrode includes a barrier layer and a main wiring layer disposed on the barrier layer,
wherein the main wiring layer includes copper or a copper alloy, and the barrier layer includes a metal oxide.

4. The thin film transistor array panel of claim 3 ,
wherein the passivation layer includes a lower passivation layer and an upper passivation layer, the lower passivation layer includes silicon oxide, and the upper passivation layer includes silicon nitride.

5. The thin film transistor array panel of claim 3 ,
wherein the metal silicide layer includes copper.

6. The thin film transistor array panel of claim 5 ,
wherein the barrier layer includes at least one of indium-zinc oxide (IZO), gallium-zinc oxide (GZO), and aluminum-zinc oxide (AZO).

7. The thin film transistor array panel of claim 1 ,
wherein the metal silicide layer is further disposed on upper surfaces of the source and drain electrodes, wherein the upper surfaces of the source and drain electrodes are not in contact with the passivation layer.

8. The thin film transistor array panel of claim 3 , further comprising a capping layer disposed on an upper surface of the main wiring layer and the capping layer includes a metal oxide, wherein the passivation layer is disposed on the capping layer without being in contact with the upper surface of the main wiring layer.

9. The thin film transistor array panel of claim 1 ,
wherein the semiconductor layer includes an oxide semiconductor.

10. The thin film transistor array panel of claim 3 ,
wherein the semiconductor layer includes a third lateral surface and the data line includes a fourth lateral surface,
wherein the third and fourth lateral surfaces are vertically aligned to each other,
wherein the third lateral surface is in contact with the passivation layer and the fourth lateral surface is in contact with the metal silicide layer without being in contact with the passivation layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Xun Zhu
• Park Jae Woo
• Song Jae Won
• Lee Keum Hee
• Choi June Whan

Classifications

• H10D64/011

  of electrodes ohmically coupled to a semiconductor · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/039

  also covering sidewalls of the conductive structures · CPC title

• H10D30/0321

  comprising silicon, e.g. amorphous silicon or polysilicon · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title