Electronic devices and methods having a compact multi-way transformer combiner

Patent metadata

Field	Value
Publication number	US-9515062-B2
Application number	US-201414575908-A
Country	US
Kind code	B2
Filing date	Dec 18, 2014
Priority date	Dec 18, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

Apparatus having structures implementing compact and symmetric multi-way transformer combiners are described herein. In an embodiment, each unit device cell of a plurality unit device cells may include two metal layers on top of the unit device cell coupled to a multi-way transformer combiner by one of the two metal layers such that the configuration of the unit device cells with the multi-way transformer combiner is symmetric. Additional apparatus, systems, and methods are disclosed.

First claim

What is claimed is:

1. An electronic device comprising:
a multi-way transformer combiner having a symmetric layout on a substrate; and
a plurality of unit device cells, each unit device cell having a structural layout within the unit device cell common to the other unit device cells of the plurality of unit device cells with respect to symmetry, each unit device cell including:
an active device; and
two metal layers on top of the unit device cell, the unit device cell coupled to the multi-way transformer combiner by one of the two metal layers to form a symmetric configuration of the unit device cells with the multi-way transformer combiner, wherein a first metal layer of the two metal layers is coupled to the active device to collect a signal from the active device, and a second metal layer of the two metal layers having an approximate 45 degree offset from the first metal layer in the unit device cell is coupled to the multi-way transformer combiner to feed the signal from the unit device cell to the multi-way transformer combiner.

2. The electronic device of claim 1 , wherein the plurality of unit device cells include a plurality of unit power amplifier cells, a plurality of unit inductor/transformer based voltage-controlled oscillator (VCO) cells, or a plurality of unit low noise amplifier cells.

3. The electronic device of claim 1 , wherein the second metal layer is configured as a straight metal line.

4. The electronic device of claim 1 , wherein the plurality of unit device cells are single-ended unit power amplifier device cells or differential unit power amplifier device cells.

5. The electronic device of claim 1 , wherein the active device includes a transistor having a gate, the gate having a gate orientation, and the first metal layer is coupled to the active device, and wherein the gate orientation of each of the plurality of unit device cells being the same.

6. The electronic device of claim 1 , wherein the multi-way transformer combiner is an octagonal multi-way transformer combiner or a square multi-way transformer combiner.

7. The electronic device of claim 1 , wherein the multi-way transformer combiner is a two-way transformer combiner, a four-way transformer combiner, or an eight-way transformer combiner, and the unit device cells are unit radio frequency (RF) power amplifier device cells.

8. The electronic device of claim 7 , wherein a number of the unit device cells are disposed inside a loop of the multi-way transformer combiner and a number of the unit device cells are disposed outside the loop of the multi-way transformer combiner.

9. An electronic device comprising:
a multi-way transformer combiner on a substrate; and
a plurality of differential unit device cells, each differential unit device cell having a structural layout within the differential unit device cell common to the other differential unit device cells of the plurality of differential unit device cells with respect to symmetry, each differential unit device cell including:
two active devices; and
two metal layers on top of the differential unit device cell with one metal layer of the two metal layers disposed over one of the two active devices and the other metal layer of the two metal layers disposed over the other of the two active devices, the two metal layers being parallel to each other, each of the two metal layers having a connection to the multi-way transformer combiner such that configuration of the differential unit device cells with the multi-way transformer combiner is substantially symmetric except for asymmetry by the connections of the differential unit device cells to the multi-way transformer combiner.

10. The electronic device of claim 9 , wherein each differential unit device cell includes a differential radio frequency (RF) power amplifier device with one of the two metal layers connected to one primary loop of the multi-way transformer combiner.

11. The electronic device of claim 9 , wherein the plurality of differential unit device cells includes the differential unit device cells configured in pairs, the differential unit device cells of each pair coupled to the multi-way transformer combiner across from each other with one of the differential unit device cells of the pair inside a loop of the multi-way transformer combiner and the other differential unit device cell of the pair outside the loop of the multi-way transformer combiner.

12. The electronic device of claim 9 , wherein the multi-way transformer combiner is an octagonal multi-way transformer combiner.

13. The electronic device of claim 9 , wherein each active device of the plurality of differential unit device cells has a gate with an orientation that is the same as the gate of the other active device of the plurality of differential unit device cells.

14. A transceiver comprising:
a transmitter having a power amplifier to provide input to circuitry of the transmitter, the power amplifier having a multi-way transformer combiner with a symmetric structural layout on a substrate, and a plurality of unit power amplifier cells coupled to the multi-way transformer combiner, each unit power amplifier cell having a structural layout within the unit power amplifier cell common to the other unit power amplifier cells of the plurality of unit power amplifier cells with respect to symmetry, each unit power amplifier cell including:
an active device; and
two metal layers on top of the unit power amplifier cell, the unit power amplifier cell coupled to the multi-way transformer combiner by one of the two metal layers such that configuration of the unit power amplifier cells with the multi-way transformer combiner is symmetric, wherein a first metal layer of the two metal layers is coupled to the active device to collect a signal from the active device and a second metal layer of the two metal layers has an approximate 45 degree offset from the first metal layer in the unit power amplifier cell and is coupled to the multi-way transformer combiner to feed the signal from the unit power amplifier cell to the multi-way transformer combiner.

15. The transceiver of claim 14 , wherein the unit power amplifier cells are single-ended unit power amplifier cells or differential unit power amplifier cells.

16. The transceiver of claim 14 , wherein the active device includes a transistor having a gate, the gate having a gate orientation, and the first metal layer is coupled to the active device, the gate orientation of each unit power amplifier cell being the same.

17. The transceiver of claim 14 , wherein the multi-way transformer combiner is an octagonal multi-way transformer combiner or a square multi-way transformer combiner.

18. The transceiver of claim 14 , wherein a number of the unit power amplifier cells are disposed inside a loop of the multi-way transformer combiner and a number of the unit power amplifier cells are disposed outside the loop of the multi-way transformer combiner.

19. The transceiver of claim 14 , wherein the transceiver is configured with an antenna coupled to the transmitter.

20. A method of forming an electronic device comprising:
forming a multi-way transformer combiner having a symmetric layout on a substrate;
forming a plurality of unit device cells each having an active device and a layout within the plurality of unit device cells common to the other unit device cells of the plurality of unit device cells with respect to symmetry; and
forming, in each unit device cell, two metal layers on top of the unit device cell, the two metal layer

Assignees

• Intel Corp

Inventors

• Xu Hongtao
• Palaskas Georgios

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H01L21/76895

  Electricity · mapped topic

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic