Multi-chip semiconductor power device

Patent metadata

Field	Value
Publication number	US-9515060-B2
Application number	US-201313847681-A
Country	US
Kind code	B2
Filing date	Mar 20, 2013
Priority date	Mar 20, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor power transistor chip having a first electrode on a first surface and a second electrode on an opposite second surface, the first semiconductor power transistor chip being mounted over a first carrier such that the second surface of the first semiconductor power transistor chip faces the first carrier and the second electrode is coupled to the first carrier;
a second semiconductor power transistor chip having a first electrode on a first surface and a second electrode on an opposite second surface, the second semiconductor power transistor chip being mounted over a second carrier such that the second surface of the second semiconductor power transistor chip faces the second carrier and the second electrode is coupled to the second carrier;
a contact clip mounted over the first semiconductor power transistor chip and over the second semiconductor power transistor chip such that the first surfaces of the first and second semiconductor power transistor chips face the contact clip and the first electrodes of the first and second semiconductor power transistor chips are coupled to the contact clip; and
a semiconductor logic chip mounted over the contact clip,
wherein the first and second semiconductor power transistor chips are arranged side by side in a first plane, the semiconductor logic chip is arranged in a second plane above the first plane, and the contact clip is arranged between the first and second planes.

2. The semiconductor device of claim 1 , wherein the contact clip has an extension in at least one lateral direction protruding beyond at least one of a laterally outer outline of the first semiconductor power chip and a laterally outer outline of the second semiconductor power chip.

3. The semiconductor device of claim 1 , wherein the first carrier and the second carrier are coplanar.

4. The semiconductor device of claim 1 , wherein the first carrier and the second carrier are chip pads of a leadframe.

5. A semiconductor device, comprising:
a first carrier having a mounting surface;
a first semiconductor power chip mounted over the mounting surface of the first carrier and having a first surface facing away from the first carrier;
a second carrier having a mounting surface;
a second semiconductor power chip mounted over the mounting surface of the second carrier and having a first surface facing away from the second carrier;
a third carrier having a mounting surface;
a connection element having a first surface connected to the first surface of the first semiconductor power chip, and a mounting surface facing away from the first surface; and
a third semiconductor chip mounted over the mounting surface of the connection element in a face-up orientation in which electrodes of the third semiconductor chip are disposed on a surface of the third semiconductor chip that is opposite the surface mounted to the connection element, and wherein the third semiconductor chip is a logic chip configured to control one or both of the first semiconductor power chip and the second semiconductor power chip,
wherein the first surface of the connection element is connected to the first surface of the second semiconductor power chip,
wherein the connection element has an extension in at least one lateral direction protruding beyond at least one of a laterally outer outline of the first semiconductor power chip and a laterally outer outline of the second semiconductor power chip,
wherein the connection element is mounted over the third carrier,
wherein the first, second and third carriers are coplanar.

6. The semiconductor device of claim 5 , wherein the connection element is a contact clip.

7. The semiconductor device of claim 5 , wherein the mounting surface of the first carrier and the mounting surface of the second carrier are coplanar.

8. The semiconductor device of claim 5 , further comprising:
an insulating layer arranged between the mounting surface of the connection element and the third semiconductor chip, the insulating layer providing a dielectric strength of greater than 100V between the mounting surface of the connection element and the third semiconductor chip.

9. The semiconductor device of claim 5 , wherein the first carrier and the second carrier are electrically disconnected from each other.

10. The semiconductor device of claim 5 , wherein a surface of the first carrier opposite to the mounting surface of the first carrier or a surface of the second carrier opposite to the mounting surface of the second carrier forms a leadless package external contact area.

11. The semiconductor device of claim 5 , wherein the semiconductor device is a DC-DC converter or an AC-DC converter.

12. The semiconductor device of claim 5 , wherein exclusively power semiconductor chips are mounted over the mounting surfaces of the first and second carriers, and wherein exclusively semiconductor logic chips are mounted over the mounting surface of the connection element.

13. The semiconductor device of claim 5 , wherein the first carrier and the second carrier are arranged side by side to each other.

14. The semiconductor device of claim 13 , wherein the first semiconductor power chip has a source electrode connected to the mounting surface of the first carrier.

15. The semiconductor device of claim 5 , further comprising:
an external terminal pad arranged side by side to the first carrier or to the second carrier, wherein the connection element is connected to the external terminal pad.

16. The semiconductor device of claim 15 , wherein the external terminal pad forms a leadless package external contact area.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Otremba Ralf
• Hoeglauer Josef
• Schloegel Xaver
• Chong Chooi Mei

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title