Chip packaging method, chip packaging module, and embedded substrate chip packaging structure
US-2024413138-A1 · Dec 12, 2024 · US
Package structure and fabrication method thereof
US9515040B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9515040-B2 |
| Application number | US-201514736436-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 11, 2015 |
| Priority date | Jul 11, 2014 |
| Publication date | Dec 6, 2016 |
| Grant date | Dec 6, 2016 |
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- Title
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Abstract
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A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal balls on the exposed portions of the metal layer; forming an encapsulant on the dielectric layer for encapsulating the electronic element and the conductive elements; removing the first carrier; and patterning the metal layer into first circuits and forming second circuits on the dielectric layer, wherein the second circuits are electrically connected to the electronic element and the first circuits. The invention dispenses with the conventional laser ablation process so as to simplify the fabrication process, save the fabrication cost and increase the product reliability.
First claim
Opening claim text (preview).
What is claimed is: 1. A package structure, comprising: an electronic element having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the electronic element and having a first surface exposing the active surface of the electronic element and a second surface opposite to the first surface; a plurality of conductive elements penetrating the first and second surfaces of the encapsulant, where…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9515040B2 cover?
- A method for fabricating a package structure is provided, including the steps of: sequentially forming a metal layer and a dielectric layer on a first carrier, wherein the dielectric layer has a plurality of openings exposing portions of the metal layer; disposing an electronic element on the dielectric layer via an active surface thereof and mounting a plurality of conductive elements of metal…
- Who is the assignee on this patent?
- Siliconware Precision Industries Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W70/09. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).