Determination of word line to word line shorts between adjacent blocks

Patent metadata

Field	Value
Publication number	US-9514835-B2
Application number	US-201414328070-A
Country	US
Kind code	B2
Filing date	Jul 10, 2014
Priority date	Jul 10, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

First claim

It is claimed:

1. A method of determining one or more defective word lines, the method comprising:
performing an inter-block stress operation on a pair of physically adjacent blocks of non-volatile memory cells of an array formed along word lines in a memory circuit, including applying a set of stress voltage levels to word lines of the pair of blocks to introduce a voltage differential between the pair of physically adjacent blocks; and
subsequently performing a defect determin…

Assignees

• Sandisk Technologies Llc

Inventors

• Magia Sagar
• Sabde Jagdish
• Nguyen Khanh

Classifications

• G11C2029/1202

  Physics · mapped topic

• H01L27/11582

  Electricity · mapped topic

• G11C29/025

  Physics · mapped topic

• H01L27/1157

  Electricity · mapped topic

• G11C16/3422 Primary

  Physics · mapped topic