Variable resistance memory device

Patent metadata

Field	Value
Publication number	US-9514807-B2
Application number	US-201514955789-A
Country	US
Kind code	B2
Filing date	Dec 1, 2015
Priority date	Dec 18, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.

First claim

What is claimed is:

1. A variable resistance memory device comprising:
upper interconnections on a substrate;
a first word line and a second word line between the substrate and the upper interconnections, the first and second word lines spaced apart from each other in a direction that is perpendicular to a top surface of the substrate;
a first bit line disposed between the first word line and the second word line, the first bit line intersecting the first and second word lines;
memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line;
a first word line contact comprising a first unitary member directly connecting the first word line to a first one of the upper interconnections, wherein the first unitary member is in direct contact with the first word line and the first one of the upper interconnections, and a lowermost surface of the first unitary member is disposed at a level higher than that of a bottom surface of the first word line from the substrate; and
a second word line contact comprising a second unitary member directly connecting the second word line to a second one of the upper interconnections, wherein the second unitary member is in direct contact with the second word line and the second one of the upper interconnections, and a lowermost surface of the second unitary member is disposed at a level higher than that of a bottom surface of the second word line from the substrate,
wherein the first word line is connected to a first peripheral circuit through the first word line contact and the first one of the upper interconnections that is connected to the first word line contact, and
wherein the second word line is connected to the first peripheral circuit through the second word line contact and the second one of the upper interconnections that is connected to the second word line contact.

2. The variable resistance memory device of claim 1 , further comprising:
a second bit line between the substrate and the upper interconnections, the second bit line spaced apart from the first bit line with the second word line interposed therebetween in the direction perpendicular to the top surface of the substrate;
a first bit line contact comprising a third unitary member directly connecting the first bit line to a third one of the upper interconnections, wherein the third unitary member is in direct contact with the first bit line and the third one of the upper interconnections, and a lowermost surface of the third unitary member is disposed at a level higher than that of a bottom surface of the first bit line from the substrate; and
a second bit line contact comprising a fourth unitary member directly connecting the second bit line to a fourth one of the upper interconnections, wherein the fourth unitary member is in direct contact with the second bit line and the fourth one of the upper interconnections, and a lowermost surface of the fourth unitary member is disposed at a level higher than that of a bottom surface of the second bit line from the substrate,
wherein the memory cells further comprise a memory cell provided in an intersecting region of the second word line and the second bit line,
wherein the first bit line is connected to a second peripheral circuit through the first bit line contact and the third one of the upper interconnections, and
wherein the second bit line is connected to the second peripheral circuit through the second bit line contact and the fourth one of the upper interconnections, and
wherein the first and second word lines or the first and second bit lines are of different lengths and are sequentially stacked in order of decreasing length away from the top surface of the substrate in the direction perpendicular thereto.

3. A variable resistance memory device comprising:
upper interconnections on a substrate;
a first word line, a second word line, and a third word line between the substrate and the upper interconnections, the first and second and third word lines spaced apart from each other in a direction that is perpendicular to a top surface of the substrate;
a first bit line disposed between the first word line and the second word line, the first bit line intersecting the first and second word lines;
a second bit line disposed between the second word line and the third word line, the second bit line intersecting the second and third word lines;
memory cells provided in an intersecting region of the first word line and the first bit line, an intersecting region of the second word line and the first bit line, an intersecting region of the second word line and the second bit line, and an intersecting region of the third word line and the second bit line;
a first word line contact comprising a unitary member directly connecting the first word line to a corresponding one of the upper interconnections;
a second word line contact comprising a unitary member directly connecting the second word line to a corresponding one of the upper interconnections;
a third word line contact comprising a unitary member directly connecting the third word line to a corresponding one of the upper interconnections;
a first bit line contact comprising a unitary member directly connecting the first bit line to a corresponding one of the upper interconnections; and
a second bit line contact comprising a unitary member directly connecting the second bit line to a corresponding one of the upper interconnections,
wherein top surfaces of the first word line contact, the second word line contact, the third word line contact, the first bit line contact, and the second bit line contact are disposed at a same distance from the substrate,
wherein bottom surfaces of the first word line contact, the second word line contact, the third word line contact, the first bit line contact, and the second bit line contact are disposed at different distances from the substrate, and
wherein the first, second, and third word lines and/or the first and second bit lines are sequentially stacked in order of decreasing length away from the top surface of the substrate in the direction perpendicular thereto.

4. The variable resistance memory device of claim 3 , further comprising:
at least one peripheral circuit configured to apply a predetermined voltage or current to each of the first word line, the second word line, the third word line, the first bit line, and the second bit line,
wherein the first word line is connected to the peripheral circuit through the first word line contact and the one of the upper interconnections that is connected to the first word line contact,
wherein the second word line is connected to the peripheral circuit through the second word line contact and the one of the upper interconnections that is connected to the second word line contact,
wherein the third word line is connected to the peripheral circuit through the third word line contact and the one of the upper interconnections that is connected to the third word line contact,
wherein the first bit line is connected to the peripheral circuit through the first bit line contact and the one of the upper interconnections that is connected to the first bit line contact, and
wherein the second bit line is connected to the peripheral circuit through the second bit line contact and the one of the upper interconnections that is connected to the second bit line contact.

5. The variable resistance memory device of claim 4 , wherein the peripheral circuit is between the substrate and a memory cell array including the memory cells, and
wherein the peripheral circuit and the memory cell array are vertically stacked on the substrate.

6. The variable resistance memory device of claim 3 , wherein the first

Assignees

• Kang Younseon
• Choi Jungdal
• Terai Masayuki
• Kim Youngbae
• Lee Jung Moo
• Jung Seungjae
• Samsung Electronics Co Ltd

Inventors

• Kang Younseon
• Choi Jungdal
• Terai Masayuki
• Kim Youngbae
• Lee Jung Moo
• Jung Seungjae

Classifications

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C8/00

  Arrangements for selecting an address in a digital store (for stores using transistors G11C11/407, G11C11/413) · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C13/0004 Primary

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/71

  Three dimensional array · CPC title