Semiconductor apparatus performing program loop by using error information and method of operating the same

Patent metadata

Field	Value
Publication number	US-9513991-B2
Application number	US-201313844910-A
Country	US
Kind code	B2
Filing date	Mar 16, 2013
Priority date	Jan 18, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device.

First claim

What is claimed is:

1. A method of operating a memory device, the method comprising:
transmitting a first page data and a second page data among a plurality of page data stored in a buffer memory block to a memory controller;
receiving, from the memory controller, the first page data and the second page data, on which an error checking and correction (ECC) operation is performed, respectively;
performing a first program loop to store the received first page data in a main memory block;
performing a second program loop to store the received second page data in the main memory block;
receiving error information of the first page data and the second page data, which is obtained through performing the ECC operation on the first page data and the second page data, respectively from a memory controller; and
performing a third program loop to store the first page data and second page data, corrected by using the received error information, in the main memory block.

2. The method of claim 1 , wherein the performing of the first program loop comprises:
transmitting the first page data to the memory controller;
receiving the first page data, on which the error checking and correction (ECC) operation performed from the memory controller; and
storing the first page data, on which the ECC operation is performed to the main memory block, and
wherein the performing of the second program loop comprising:
transmitting the second page data to the memory controller;
receiving the second page data, on which the ECC operation is performed from the controller; and
storing the second page data, on which the ECC operation is performed in the main memory block.

3. The method of claim 1 , wherein the error information comprises a location and a correction value of an error bit included in the first page data and the second page data.

4. The method of claim 1 , wherein the error information comprises a column address and a corrected bit of an error bit included in the first page data and the second page data.

5. The method of claim 1 , wherein the first page data includes a least significant bit (LSB) data and the second page data includes a most significant bit (MSB) data, and
the third program loop is performed to re-program the LSB data and the MSB data.

6. The method of claim 1 , wherein the correcting of the first page data and the second page data includes performing an exclusive OR (XOR) operation on the first page data and the second page data using the error information.

7. The method of claim 1 , wherein the first and the second program loop is performed to set threshold voltages of memory cells of a selected word line in the main memory block to be lower than target levels of the memory cells by set values, and
the third program loop is performed to set the threshold voltages of memory cells of the selected word line in the main memory block to be higher or equal to the target levels of the memory cells.

8. A method of operating a memory device, the method comprising:
transmitting a first page data, a second page data and the third page data among a plurality of page data stored in a buffer memory block to a memory controller;
receiving, from the memory controller, the first page data, the second page data and the third page data, on which an error checking and correction (ECC) operation is performed, respectively;
performing a first program loop to store the first page data, the second page data and the third page data, on which the ECC operation is performed in a main memory block of the memory device;
receiving, from the memory controller, error information of the first page data, the second page data and the third page data, which is obtained through performing the ECC operation on the first page data, the second page data and the third page data, respectively; and
performing a second program loop to store the first page data, the second page data and the third page data, corrected by using the error information, in a main memory block of the memory device.

9. The method of claim 8 , wherein the error information includes a location and a correction value of an error bit included in the first page data and the second page data.

10. The method of claim 8 , wherein the error information includes a column address and a corrected bit of an error bit included in the first page data and the second page data.

11. The method of claim 8 , wherein the performing of the second program loop comprises:
correcting the first page data, the second page data and the third page data by using the error information, respectively; and
storing the corrected first page data, the corrected second page data and the corrected third page data in the main memory block of the memory device.

12. The method of claim 11 , wherein the correcting the first page data, the second page data and the third page data comprises performing an exclusive OR (XOR) operation using the error information to the first page data, the second page data and the third page data.

13. The method of claim 8 , wherein first page data includes a least significant bit (LSB) data, the second page data includes a most significant bit (MSB) data, and the third page data includes a center significant bit (CSB) data.

14. The method of claim 8 , wherein the first program loop is performed to set threshold voltages of memory cells of a selected word line in the main memory block to be lower than target levels of the memory cells by set values, and
the second program loop is performed to set the threshold voltages of memory cells of the selected word line in the main memory block to be higher or equal to the target levels of the memory cells.

Assignees

• Sk Hynix Inc

Inventors

• Rho Jun Rye

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title