Vector friendly instruction format and execution thereof

Patent metadata

Field	Value
Publication number	US-9513917-B2
Application number	US-201414170397-A
Country	US
Kind code	B2
Filing date	Jan 31, 2014
Priority date	Apr 1, 2011
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

First claim

What is claimed is:

1. An apparatus comprising:
an instruction converter to convert each occurrence of an instruction of a first instruction set that has a first instruction format into one or more corresponding instructions of a second different instruction set, wherein the first instruction format includes a first plurality of templates that each include a plurality of fields including a base operation field, a data element width (W) field, a vector length field, a write mask control field, and a write mask field, wherein the first instruction format supports through different values in the base operation field specification of a plurality of different vector operations, wherein each of the plurality of vector operations requires an operation to be independently performed on each of a plurality of different data element positions of at least one source vector operand to generate at least one destination vector operand, wherein the first instruction format supports through different values in the data element width field specification of a 32 bit and a 64 bit data element width, wherein the first plurality of templates support through different values in the vector length field specification of a plurality of different vector lengths, wherein the first instruction format supports through different values in the write mask field specification of different write masks, wherein the first instruction format supports through different values in the write mask control field selection between merging write mask and zeroing write mask, wherein only one of the different values is placed in each of the base operation field, the data element width field, the write mask control field, and the write mask field on each said occurrence of the instruction in the first instruction format in instruction streams,
the instruction converter to convert the occurrences of the instructions that have the first instruction format that includes the first plurality of templates as follows:
distinguish, for each of the occurrences, which one of the different vector operations to perform based on the base operation field's content;
distinguish, for each of the occurrences, which one of the data element widths to use based on the data element width field's content;
distinguish, for each of the occurrences, which one of the vector lengths to use based on the vector length field's content;
distinguish, for each of the occurrences which one of merging write mask and zeroing write mask to perform based on the write mask control field's content; and
distinguish, for each of the occurrences, which one of the different write masks to use based on the write mask field's content, wherein the data element width and the vector length for the occurrence distinguishes which data element positions correspond with which bits of the occurrence's write mask, wherein the write mask for the occurrence specifies on a per data element position basis whether results of the occurrence's vector operation are or are not to be reflected in the destination vector operand's corresponding data element positions, wherein those of the destination vector operand's corresponding data element positions that correspond to bits of the occurrence's write mask that have a non-zero value reflect the results of the occurrence's vector operation, and wherein those of the destination vector operand's corresponding data element positions that correspond to bits of the occurrence's write mask that have a zero value are set to zero when zeroing write mask is selected; and

a processor coupled with the instruction converter, the processor to decode and execute the one or more instructions converted from each occurrence of the instruction of the first instruction set that has the first instruction format.

2. The apparatus of claim 1 , wherein the plurality of different vector lengths includes 128, 256, and 512 bits.

3. The apparatus of claim 1 , wherein the first instruction format also supports, through different values in the data element width field, the specification of an 8 bit and a 16 bit data element width.

4. The apparatus of claim 1 , wherein the first instruction format also supports, through different values in a real opcode field inside the base operation field, specification of an 8 bit and a 16 bit data element width.

5. The apparatus of claim 1 , wherein one of the different values for the write mask field is reserved to indicate that all of the results of the occurrence's vector operation are to be reflected in the destination vector operand's corresponding data element positions.

6. The apparatus of claim 5 , wherein others of the different values for the write mask field distinguish different write mask registers to store configurable write masks.

7. The apparatus of claim 1 , wherein the first instruction format supports operations on two source vector operands and the destination vector operand does not overwrite either of the two source vector operands.

8. The apparatus of claim 1 , wherein the first instruction format supports operations on two source vector operands and the destination vector operand overwrites one of the two source vector operands.

9. An apparatus comprising:
an instruction converter to convert an instruction that has a vector friendly instruction format, and is of a first instruction set, to one or more instructions of a second different instruction set, wherein the first instruction set includes a plurality of instruction formats including the vector friendly instruction format, wherein vector instructions in the vector friendly instruction format specify vector operations that each generate a destination vector operand that is to have a plurality of data elements at different data element positions, wherein the vector friendly instruction format includes the following fields of the following size and in the following order:
a one byte format field to store a value that uniquely identifies the vector friendly instruction format;
a one bit R field to store a bit that is combined with a first set of three lower order bits to address a plurality of architectural vector registers for certain instructions in the vector friendly instruction format;
a one bit X field to store a bit that is combined with a second set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format;
a one bit B field to store a bit that is combined with a third set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format;
a one bit R′ field to store a bit that is added as a most significant bit to the combination of the R field's bit and the first set of three lower order bits to address the architectural vector registers for certain instructions in the vector friendly instruction format;
a four bit opcode map that is part of a base operation field;
a one bit data element width (W) field to store a bit to distinguish between a 32 bit data element size and a 64 bit data element size for certain instructions in the vector friendly instruction format;
a four bit V field to store a low order four bits used to address the architectural vector registers for certain instructions in the vector friendly instruction format;
a one bit class (U) field to store a bit used to distinguish between two classes of instruction templates;
a two bit prefix encoding field that is part of the base operation field;
a one bit alpha field that is interpreted as a round type operation field, a data transform type operation field, an eviction hint field, a write mask control field, or a reserved field, wherein the write mask control field's content selects between

Assignees

• Intel Corp

Inventors

• Valentine Robert C
• San Adrian Jesus Corbal
• Sans Roger Espasa
• Cavin Robert D
• Toll Bret L
• Duran Santiago Galan
• Wiedemeier Jeffrey G
• Samudrala Sridhar
• Girkar Milind Baburao
• Grochowski Edward Thomas
• Hall Jonathan Cannon
• Bradford Dennis R
• Ould-Ahmed-Vall Elmoustapha
• Abel James C
• Charney Mark
• Abraham Seth
• Sair Suleyman
• Forsyth Andrew Thomas
• Wu Lisa
• Yount Charles

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D48/30

  Devices controlled by electric currents or voltages · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title