Memory management based on usage specifications

Patent metadata

Field	Value
Publication number	US-9513815-B2
Application number	US-201414523006-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Dec 19, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A method is provided for managing a memory device including a plurality of physical memory segments. A logical memory space is classified into a plurality of classifications based on usage specifications. The plurality of physical memory segments is allocated to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments. A data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments. The plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification. Logical addresses having the second classification can be redirected to physical segments allocated to logical addresses having the first classification, and the data structure can be updated to record redirected logical addresses. A free command can release a physical memory segment allocated for main memory use.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory device including a plurality of physical memory segments; and
a memory controller coupled to the memory device, including:
logic to classify a logical memory space into a plurality of classifications based on usage specifications, wherein the plurality of classifications includes a first classification and a second classification haying different usage statistic requirements than the first classification;
logic to allocate the plurality of physical memory segments to corresponding logical addresses based on the plurality of classifications, and on usage statistics of the physical memory segments;
logic to receive a command to free a logical memory segment having a first logical segment number relative to a starting logical segment number for logical memory segments in the logical memory space;
logic to derive a second logical segment number based on the first logical segment number and the starting logical segment number;
logic to translate the second logical segment number to a physical segment number;
logic to release a physical memory segment having the physical segment number in the plurality of physical memory segments; and
logic to redirect logical addresses having the second classification to physical segments allocated to logical addresses having the first classification, and to update a data structure to record redirected logical addresses, wherein the data structure is maintained recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments.

2. The apparatus of claim 1 , wherein the memory controller includes:
logic to maintain a data structure recording translation between logical addresses in the logical memory space and physical addresses of the physical memory segments.

3. The apparatus of claim 1 , wherein the memory controller includes:
logic to maintain a plurality of sets of buckets of free memory segments based on usage statistics of the free memory segments; and
logic to allocate a free memory segment to logical address in a particular classification in the plurality of classifications in a bucket corresponding to usage statistics that match the particular classification, and to remove the free memory segment from the bucket after said allocating.

4. The apparatus of claim 3 , wherein the memory controller includes:
logic to deallocate a physical memory segment, and to add the physical memory segment to a bucket in a set in the plurality of sets of buckets,
wherein the physical memory segment has a usage statistic matching the usage statistics of the bucket to which it is added.

5. The apparatus of claim 1 , wherein the logic to find and allocate includes:
in response to a request to allocate a free memory segment to a logical memory segment having the first classification,
logic to search for the free memory segment having a write count matching the first classification and lower than write counts of other free memory segments matching the first classification;
logic to, if the free memory segment is found, allocate the free memory segment to the logical memory segment, otherwise search for a second free memory segment having a second write count matching the second classification and higher than write counts of other free memory segments matching the second classification; and
logic to, if the second free memory segment is found, allocate the second free memory segment to the logical memory segment having the first classification.

6. The apparatus of claim 1 , wherein the memory controller includes:
logic to search for a free memory segment having a write count matching the second classification and lower than other write counts of free memory segments matching the second classification;
logic to, if the free memory segment is found, allocate the free memory segment to the logical memory segment, otherwise search for a second memory segment having a write count matching the first classification and lower than write counts of other memory segments matching the first classification; and
logic to, if the second memory segment is found, search for a second free memory segment having a write count matching the first classification, move data in the second memory segment to the second free memory segment, and then re-allocate the second memory segment to the logical memory segment having the second classification.

7. The apparatus of claim 1 , wherein the memory controller includes:
logic responsive to a request to write to a physical memory segment allocated to a logical memory segment having the first classification, to update usage statistics of the physical memory segment; and
logic to, if the updated usage statistics have a write count higher than a discarding threshold, allocate a free memory segment having a second write count lower than the discarding threshold to the logical memory segment; and discard the physical memory segment.

8. The apparatus of claim 1 , wherein the memory controller includes:
logic responsive to a request to write to a physical memory segment allocated to a logical memory segment having the second classification to update usage statistics of the physical memory segment; and
logic to, if the updated usage statistics have a write count higher than a downgrading threshold, allocate a free memory segment having a second write count lower than the downgrading threshold to the logical memory segment.

9. The apparatus of claim 1 , wherein the memory controller includes:
logic responsive to a request to link a first range of logical addresses having the first classification to a second range of logical addresses having the second classification to,
if a physical memory segment is not allocated to a logical memory segment in the first range of logical addresses or the second range of logical addresses, allocate a free physical memory segment to the logical memory segment;
logic to set indicators that indicate that the second range of logical addresses having the second classification is redirected; and
logic to set linking information that redirects the second range of logical addresses having the second classification to physical segments allocated to the first range of logical addresses having the first classification.

10. The apparatus of claim 1 , wherein the memory controller includes:
logic responsive to a request to unlink a range of logical addresses having the second classification from physical segments allocated to logical addresses having the first classification to reset indicators that indicate that the range of logical addresses having the second classification is redirected; and
logic to reset linking information that redirects the range of logical addresses having the second classification.

11. The apparatus of claim 1 , wherein the memory device is on an integrated circuit, and the memory controller comprises logic on the integrated circuit.

12. The apparatus of claim 1 , wherein the memory device comprises memory cells including phase change memory materials.

13. A method for operating a memory device including a plurality of physical memory segments, comprising:
classifying logical addresses in a logical memory space into a plurality of classifications based on usage specifications, wherein the plurality of classifications includes a first classification and a second classification having different usage statistic requirements than the first classification, using logic controlling the memory;
allocating the plurality of physical memory segments to corresponding logical addresses based on the plurality of classifications, and on

Assignees

• Macronix Int Co Ltd

Inventors

• Chang Ping-Chun
• Chang Yuan-Hao
• Chang Hung-Sheng
• Kuo Tei-Wei
• Li Hsiang-Pang

Classifications

• G06F2212/202

  Non-volatile memory · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F12/023

  Free address space management · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title